Lines Matching +full:i2c +full:- +full:transfer +full:- +full:timeout +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
14 #include <linux/dma-mapping.h>
16 #include <linux/i2c.h>
70 /* I2C mini core related values */
125 /* Maximum transfer length for single DMA descriptor */
128 /* Maximum transfer length for all DMA descriptors */
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
145 * data transfer
164 * total_tx_len: total tx length including tag bytes for current QUP transfer
165 * total_rx_len: total rx length including tag bytes for current QUP transfer
184 * tags: contains tx tag bytes for current QUP transfer
246 /* I2C protocol errors */
260 /* To check if the current transfer is using DMA */
276 /* function to write tags in tx fifo for i2c read transfer */
283 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_interrupt()
288 bus_err = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
289 qup_err = readl(qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
290 opflags = readl(qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
292 if (!qup->msg) { in qup_i2c_interrupt()
294 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
303 writel(qup_err, qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt()
307 writel(bus_err, qup->base + QUP_I2C_STATUS); in qup_i2c_interrupt()
311 * transfer. In Error case, sometimes, QUP generates more than one in qup_i2c_interrupt()
314 if (qup->use_dma && (qup->qup_err || qup->bus_err)) in qup_i2c_interrupt()
321 * flush operation needs to be scheduled in transfer function in qup_i2c_interrupt()
325 if (!qup->use_dma) in qup_i2c_interrupt()
326 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt()
331 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
334 blk->tx_fifo_free += qup->out_blk_sz; in qup_i2c_interrupt()
335 if (qup->msg->flags & I2C_M_RD) in qup_i2c_interrupt()
336 qup->write_rx_tags(qup); in qup_i2c_interrupt()
338 qup->write_tx_fifo(qup); in qup_i2c_interrupt()
343 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt()
345 if (!blk->is_rx_blk_mode) { in qup_i2c_interrupt()
346 blk->fifo_available += qup->in_fifo_sz; in qup_i2c_interrupt()
347 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
349 blk->fifo_available += qup->in_blk_sz; in qup_i2c_interrupt()
350 qup->read_rx_fifo(qup); in qup_i2c_interrupt()
354 if (qup->msg->flags & I2C_M_RD) { in qup_i2c_interrupt()
355 if (!blk->rx_bytes_read) in qup_i2c_interrupt()
365 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE)) in qup_i2c_interrupt()
370 qup->qup_err = qup_err; in qup_i2c_interrupt()
371 qup->bus_err = bus_err; in qup_i2c_interrupt()
372 complete(&qup->xfer); in qup_i2c_interrupt()
383 * State transition takes 3 AHB clocks cycles + 3 I2C master clock in qup_i2c_poll_state_mask()
384 * cycles. So retry once after a 1uS delay. in qup_i2c_poll_state_mask()
387 state = readl(qup->base + QUP_STATE); in qup_i2c_poll_state_mask()
394 } while (retries--); in qup_i2c_poll_state_mask()
396 return -ETIMEDOUT; in qup_i2c_poll_state_mask()
406 u32 val = readl(qup->base + QUP_STATE); in qup_i2c_flush()
409 writel(val, qup->base + QUP_STATE); in qup_i2c_flush()
425 return -EIO; in qup_i2c_change_state()
427 writel(state, qup->base + QUP_STATE); in qup_i2c_change_state()
430 return -EIO; in qup_i2c_change_state()
434 /* Check if I2C bus returns to IDLE state */
437 unsigned long timeout; in qup_i2c_bus_active() local
441 timeout = jiffies + len * 4; in qup_i2c_bus_active()
443 status = readl(qup->base + QUP_I2C_STATUS); in qup_i2c_bus_active()
447 if (time_after(jiffies, timeout)) in qup_i2c_bus_active()
448 ret = -ETIMEDOUT; in qup_i2c_bus_active()
458 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v1()
459 struct i2c_msg *msg = qup->msg; in qup_i2c_write_tx_fifo_v1()
465 if (qup->pos == 0) { in qup_i2c_write_tx_fifo_v1()
468 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
474 while (blk->tx_fifo_free && qup->pos < msg->len) { in qup_i2c_write_tx_fifo_v1()
475 if (qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
481 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT; in qup_i2c_write_tx_fifo_v1()
483 val = qup_tag | msg->buf[qup->pos]; in qup_i2c_write_tx_fifo_v1()
486 if (idx & 1 || qup->pos == msg->len - 1) in qup_i2c_write_tx_fifo_v1()
487 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v1()
489 qup->pos++; in qup_i2c_write_tx_fifo_v1()
491 blk->tx_fifo_free--; in qup_i2c_write_tx_fifo_v1()
498 qup->blk.pos = 0; in qup_i2c_set_blk_data()
499 qup->blk.data_len = msg->len; in qup_i2c_set_blk_data()
500 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit); in qup_i2c_set_blk_data()
507 if (qup->blk.data_len > qup->blk_xfer_limit) in qup_i2c_get_data_len()
508 data_len = qup->blk_xfer_limit; in qup_i2c_get_data_len()
510 data_len = qup->blk.data_len; in qup_i2c_get_data_len()
517 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN)); in qup_i2c_check_msg_len()
525 if (qup->is_smbus_read) { in qup_i2c_set_tags_smb()
532 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags_smb()
549 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last); in qup_i2c_set_tags()
555 if (qup->blk.pos == 0) { in qup_i2c_set_tags()
559 if (msg->flags & I2C_M_TEN) in qup_i2c_set_tags()
565 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
570 if (msg->flags & I2C_M_RD) in qup_i2c_set_tags()
571 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ? in qup_i2c_set_tags()
594 complete(&qup->xfer); in qup_i2c_bam_cb()
604 ret = dma_map_sg(qup->dev, sg, 1, dir); in qup_sg_set_buf()
606 return -EINVAL; in qup_sg_set_buf()
613 if (qup->btx.dma) in qup_i2c_rel_dma()
614 dma_release_channel(qup->btx.dma); in qup_i2c_rel_dma()
615 if (qup->brx.dma) in qup_i2c_rel_dma()
616 dma_release_channel(qup->brx.dma); in qup_i2c_rel_dma()
617 qup->btx.dma = NULL; in qup_i2c_rel_dma()
618 qup->brx.dma = NULL; in qup_i2c_rel_dma()
625 if (!qup->btx.dma) { in qup_i2c_req_dma()
626 qup->btx.dma = dma_request_chan(qup->dev, "tx"); in qup_i2c_req_dma()
627 if (IS_ERR(qup->btx.dma)) { in qup_i2c_req_dma()
628 err = PTR_ERR(qup->btx.dma); in qup_i2c_req_dma()
629 qup->btx.dma = NULL; in qup_i2c_req_dma()
630 dev_err(qup->dev, "\n tx channel not available"); in qup_i2c_req_dma()
635 if (!qup->brx.dma) { in qup_i2c_req_dma()
636 qup->brx.dma = dma_request_chan(qup->dev, "rx"); in qup_i2c_req_dma()
637 if (IS_ERR(qup->brx.dma)) { in qup_i2c_req_dma()
638 dev_err(qup->dev, "\n rx channel not available"); in qup_i2c_req_dma()
639 err = PTR_ERR(qup->brx.dma); in qup_i2c_req_dma()
640 qup->brx.dma = NULL; in qup_i2c_req_dma()
655 qup->blk_xfer_limit = QUP_READ_LIMIT; in qup_i2c_bam_make_desc()
658 blocks = qup->blk.count; in qup_i2c_bam_make_desc()
659 rem = msg->len - (blocks - 1) * limit; in qup_i2c_bam_make_desc()
661 if (msg->flags & I2C_M_RD) { in qup_i2c_bam_make_desc()
662 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
663 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
664 tags = &qup->start_tag.start[qup->tag_buf_pos + len]; in qup_i2c_bam_make_desc()
666 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
669 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
670 &qup->brx.tag.start[0], in qup_i2c_bam_make_desc()
676 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++], in qup_i2c_bam_make_desc()
677 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
684 qup->blk.pos = i; in qup_i2c_bam_make_desc()
686 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
687 &qup->start_tag.start[qup->tag_buf_pos], in qup_i2c_bam_make_desc()
692 qup->tag_buf_pos += len; in qup_i2c_bam_make_desc()
694 while (qup->blk.pos < blocks) { in qup_i2c_bam_make_desc()
695 tlen = (i == (blocks - 1)) ? rem : limit; in qup_i2c_bam_make_desc()
696 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len]; in qup_i2c_bam_make_desc()
698 qup->blk.data_len -= tlen; in qup_i2c_bam_make_desc()
700 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
707 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++], in qup_i2c_bam_make_desc()
708 &msg->buf[limit * i], in qup_i2c_bam_make_desc()
713 qup->blk.pos = i; in qup_i2c_bam_make_desc()
716 qup->tag_buf_pos += tx_len; in qup_i2c_bam_make_desc()
728 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt; in qup_i2c_bam_schedule_desc()
730 /* schedule the EOT and FLUSH I2C tags */ in qup_i2c_bam_schedule_desc()
733 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT; in qup_i2c_bam_schedule_desc()
737 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++], in qup_i2c_bam_schedule_desc()
738 &qup->brx.tag.start[0], in qup_i2c_bam_schedule_desc()
744 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP; in qup_i2c_bam_schedule_desc()
745 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0], in qup_i2c_bam_schedule_desc()
750 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt, in qup_i2c_bam_schedule_desc()
754 dev_err(qup->dev, "failed to get tx desc\n"); in qup_i2c_bam_schedule_desc()
755 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
760 txd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
761 txd->callback_param = qup; in qup_i2c_bam_schedule_desc()
766 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
770 dma_async_issue_pending(qup->btx.dma); in qup_i2c_bam_schedule_desc()
773 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg, in qup_i2c_bam_schedule_desc()
777 dev_err(qup->dev, "failed to get rx desc\n"); in qup_i2c_bam_schedule_desc()
778 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
781 dmaengine_terminate_sync(qup->btx.dma); in qup_i2c_bam_schedule_desc()
785 rxd->callback = qup_i2c_bam_cb; in qup_i2c_bam_schedule_desc()
786 rxd->callback_param = qup; in qup_i2c_bam_schedule_desc()
789 ret = -EINVAL; in qup_i2c_bam_schedule_desc()
793 dma_async_issue_pending(qup->brx.dma); in qup_i2c_bam_schedule_desc()
796 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) in qup_i2c_bam_schedule_desc()
797 ret = -ETIMEDOUT; in qup_i2c_bam_schedule_desc()
799 if (ret || qup->bus_err || qup->qup_err) { in qup_i2c_bam_schedule_desc()
800 reinit_completion(&qup->xfer); in qup_i2c_bam_schedule_desc()
804 dev_err(qup->dev, "change to run state timed out"); in qup_i2c_bam_schedule_desc()
811 if (!wait_for_completion_timeout(&qup->xfer, HZ)) in qup_i2c_bam_schedule_desc()
812 dev_err(qup->dev, "flush timed out\n"); in qup_i2c_bam_schedule_desc()
814 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_bam_schedule_desc()
818 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE); in qup_i2c_bam_schedule_desc()
821 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt, in qup_i2c_bam_schedule_desc()
829 qup->btx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
830 qup->brx.sg_cnt = 0; in qup_i2c_bam_clear_tag_buffers()
831 qup->tag_buf_pos = 0; in qup_i2c_bam_clear_tag_buffers()
841 enable_irq(qup->irq); in qup_i2c_bam_xfer()
847 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_bam_xfer()
848 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_bam_xfer()
851 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE); in qup_i2c_bam_xfer()
854 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK); in qup_i2c_bam_xfer()
861 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_bam_xfer()
865 qup->msg = msg + idx; in qup_i2c_bam_xfer()
866 qup->is_last = idx == (num - 1); in qup_i2c_bam_xfer()
868 ret = qup_i2c_bam_make_desc(qup, qup->msg); in qup_i2c_bam_xfer()
873 * Make DMA descriptor and schedule the BAM transfer if its in qup_i2c_bam_xfer()
879 if (qup->btx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
880 qup->brx.sg_cnt > qup->max_xfer_sg_len || in qup_i2c_bam_xfer()
881 qup->is_last) { in qup_i2c_bam_xfer()
891 disable_irq(qup->irq); in qup_i2c_bam_xfer()
893 qup->msg = NULL; in qup_i2c_bam_xfer()
903 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout); in qup_i2c_wait_for_complete()
905 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_wait_for_complete()
906 ret = -ETIMEDOUT; in qup_i2c_wait_for_complete()
909 if (qup->bus_err || qup->qup_err) in qup_i2c_wait_for_complete()
910 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO; in qup_i2c_wait_for_complete()
917 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v1()
918 struct i2c_msg *msg = qup->msg; in qup_i2c_read_rx_fifo_v1()
922 while (blk->fifo_available && qup->pos < msg->len) { in qup_i2c_read_rx_fifo_v1()
925 val = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_read_rx_fifo_v1()
926 msg->buf[qup->pos++] = val & 0xFF; in qup_i2c_read_rx_fifo_v1()
928 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT; in qup_i2c_read_rx_fifo_v1()
931 blk->fifo_available--; in qup_i2c_read_rx_fifo_v1()
934 if (qup->pos == msg->len) in qup_i2c_read_rx_fifo_v1()
935 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v1()
940 struct i2c_msg *msg = qup->msg; in qup_i2c_write_rx_tags_v1()
946 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len; in qup_i2c_write_rx_tags_v1()
949 writel(val, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v1()
954 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_v1()
958 blk->is_tx_blk_mode = blk->total_tx_len > qup->out_fifo_sz; in qup_i2c_conf_v1()
959 blk->is_rx_blk_mode = blk->total_rx_len > qup->in_fifo_sz; in qup_i2c_conf_v1()
961 if (blk->is_tx_blk_mode) { in qup_i2c_conf_v1()
963 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
964 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
966 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_v1()
967 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_v1()
970 if (blk->total_rx_len) { in qup_i2c_conf_v1()
971 if (blk->is_rx_blk_mode) { in qup_i2c_conf_v1()
973 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
974 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
976 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_v1()
977 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_v1()
983 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_v1()
984 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_v1()
989 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v1()
990 blk->fifo_available = 0; in qup_i2c_clear_blk_v1()
991 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v1()
996 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v1()
1005 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v1()
1011 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v1()
1012 enable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1013 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v1()
1014 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v1()
1026 ret = qup_i2c_wait_for_complete(qup, qup->msg); in qup_i2c_conf_xfer_v1()
1033 disable_irq(qup->irq); in qup_i2c_conf_xfer_v1()
1039 struct i2c_msg *msg = qup->msg; in qup_i2c_write_one()
1040 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_one()
1042 qup->pos = 0; in qup_i2c_write_one()
1043 blk->total_tx_len = msg->len + 1; in qup_i2c_write_one()
1044 blk->total_rx_len = 0; in qup_i2c_write_one()
1051 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_one()
1053 qup->pos = 0; in qup_i2c_read_one()
1054 blk->total_tx_len = 2; in qup_i2c_read_one()
1055 blk->total_rx_len = qup->msg->len; in qup_i2c_read_one()
1067 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer()
1071 qup->bus_err = 0; in qup_i2c_xfer()
1072 qup->qup_err = 0; in qup_i2c_xfer()
1074 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer()
1079 /* Configure QUP as I2C mini core */ in qup_i2c_xfer()
1080 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); in qup_i2c_xfer()
1084 ret = -EIO; in qup_i2c_xfer()
1089 ret = -EINVAL; in qup_i2c_xfer()
1093 qup->msg = &msgs[idx]; in qup_i2c_xfer()
1111 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer()
1112 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer()
1119 * before each i2c sub transfer.
1123 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_count_v2()
1126 if (blk->is_tx_blk_mode) in qup_i2c_conf_count_v2()
1127 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1128 qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_count_v2()
1130 writel(qup->config_run | blk->total_tx_len, in qup_i2c_conf_count_v2()
1131 qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_count_v2()
1133 if (blk->total_rx_len) { in qup_i2c_conf_count_v2()
1134 if (blk->is_rx_blk_mode) in qup_i2c_conf_count_v2()
1135 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1136 qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_count_v2()
1138 writel(qup->config_run | blk->total_rx_len, in qup_i2c_conf_count_v2()
1139 qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_count_v2()
1144 writel(qup_config, qup->base + QUP_CONFIG); in qup_i2c_conf_count_v2()
1148 * Configure registers related with transfer mode (FIFO/Block)
1149 * before starting of i2c transfer. It will be called only once in
1154 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_mode_v2()
1157 if (blk->is_tx_blk_mode) { in qup_i2c_conf_mode_v2()
1159 writel(0, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_conf_mode_v2()
1161 writel(0, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_conf_mode_v2()
1164 if (blk->is_rx_blk_mode) { in qup_i2c_conf_mode_v2()
1166 writel(0, qup->base + QUP_MX_READ_CNT); in qup_i2c_conf_mode_v2()
1168 writel(0, qup->base + QUP_MX_INPUT_CNT); in qup_i2c_conf_mode_v2()
1171 writel(io_mode, qup->base + QUP_IO_MODE); in qup_i2c_conf_mode_v2()
1174 /* Clear required variables before starting of any QUP v2 sub transfer. */
1177 blk->send_last_word = false; in qup_i2c_clear_blk_v2()
1178 blk->tx_tags_sent = false; in qup_i2c_clear_blk_v2()
1179 blk->tx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1180 blk->tx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1181 blk->tx_fifo_free = 0; in qup_i2c_clear_blk_v2()
1183 blk->rx_tags_fetched = false; in qup_i2c_clear_blk_v2()
1184 blk->rx_bytes_read = false; in qup_i2c_clear_blk_v2()
1185 blk->rx_fifo_data = 0; in qup_i2c_clear_blk_v2()
1186 blk->rx_fifo_data_pos = 0; in qup_i2c_clear_blk_v2()
1187 blk->fifo_available = 0; in qup_i2c_clear_blk_v2()
1190 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1193 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_data()
1196 for (j = blk->rx_fifo_data_pos; in qup_i2c_recv_data()
1197 blk->cur_blk_len && blk->fifo_available; in qup_i2c_recv_data()
1198 blk->cur_blk_len--, blk->fifo_available--) { in qup_i2c_recv_data()
1200 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_data()
1202 *(blk->cur_data++) = blk->rx_fifo_data; in qup_i2c_recv_data()
1203 blk->rx_fifo_data >>= 8; in qup_i2c_recv_data()
1211 blk->rx_fifo_data_pos = j; in qup_i2c_recv_data()
1214 /* Receive tags for read message in QUP v2 i2c transfer. */
1217 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_recv_tags()
1219 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE); in qup_i2c_recv_tags()
1220 blk->rx_fifo_data >>= blk->rx_tag_len * 8; in qup_i2c_recv_tags()
1221 blk->rx_fifo_data_pos = blk->rx_tag_len; in qup_i2c_recv_tags()
1222 blk->fifo_available -= blk->rx_tag_len; in qup_i2c_recv_tags()
1235 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_read_rx_fifo_v2()
1237 if (!blk->rx_tags_fetched) { in qup_i2c_read_rx_fifo_v2()
1239 blk->rx_tags_fetched = true; in qup_i2c_read_rx_fifo_v2()
1243 if (!blk->cur_blk_len) in qup_i2c_read_rx_fifo_v2()
1244 blk->rx_bytes_read = true; in qup_i2c_read_rx_fifo_v2()
1248 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1255 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_blk_data()
1258 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free; in qup_i2c_write_blk_data()
1259 (*len)--, blk->tx_fifo_free--) { in qup_i2c_write_blk_data()
1260 blk->tx_fifo_data |= *(*data)++ << (j * 8); in qup_i2c_write_blk_data()
1262 writel(blk->tx_fifo_data, in qup_i2c_write_blk_data()
1263 qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_blk_data()
1264 blk->tx_fifo_data = 0x0; in qup_i2c_write_blk_data()
1271 blk->tx_fifo_data_pos = j; in qup_i2c_write_blk_data()
1274 /* Transfer tags for read message in QUP v2 i2c transfer. */
1277 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_rx_tags_v2()
1279 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len); in qup_i2c_write_rx_tags_v2()
1280 if (blk->tx_fifo_data_pos) in qup_i2c_write_rx_tags_v2()
1281 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_rx_tags_v2()
1308 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_write_tx_fifo_v2()
1310 if (!blk->tx_tags_sent) { in qup_i2c_write_tx_fifo_v2()
1311 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, in qup_i2c_write_tx_fifo_v2()
1312 &blk->tx_tag_len); in qup_i2c_write_tx_fifo_v2()
1313 blk->tx_tags_sent = true; in qup_i2c_write_tx_fifo_v2()
1316 if (blk->send_last_word) in qup_i2c_write_tx_fifo_v2()
1319 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len); in qup_i2c_write_tx_fifo_v2()
1320 if (!blk->cur_blk_len) { in qup_i2c_write_tx_fifo_v2()
1321 if (!blk->tx_fifo_data_pos) in qup_i2c_write_tx_fifo_v2()
1324 if (blk->tx_fifo_free) in qup_i2c_write_tx_fifo_v2()
1327 blk->send_last_word = true; in qup_i2c_write_tx_fifo_v2()
1333 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE); in qup_i2c_write_tx_fifo_v2()
1337 * Main transfer function which read or write i2c data.
1338 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1345 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_conf_xfer_v2()
1346 struct i2c_msg *msg = qup->msg; in qup_i2c_conf_xfer_v2()
1355 if (qup->is_smbus_read) { in qup_i2c_conf_xfer_v2()
1361 blk->cur_data += 1; in qup_i2c_conf_xfer_v2()
1368 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN; in qup_i2c_conf_xfer_v2()
1373 /* If it is first sub transfer, then configure i2c bus clocks */ in qup_i2c_conf_xfer_v2()
1379 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); in qup_i2c_conf_xfer_v2()
1386 reinit_completion(&qup->xfer); in qup_i2c_conf_xfer_v2()
1387 enable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1392 if (!blk->is_tx_blk_mode) { in qup_i2c_conf_xfer_v2()
1393 blk->tx_fifo_free = qup->out_fifo_sz; in qup_i2c_conf_xfer_v2()
1417 disable_irq(qup->irq); in qup_i2c_conf_xfer_v2()
1422 * Transfer one read/write message in i2c transfer. It splits the message into
1430 struct i2c_msg *msg = qup->msg; in qup_i2c_xfer_v2_msg()
1431 struct qup_i2c_block *blk = &qup->blk; in qup_i2c_xfer_v2_msg()
1432 u8 *msg_buf = msg->buf; in qup_i2c_xfer_v2_msg()
1434 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT; in qup_i2c_xfer_v2_msg()
1437 for (i = 0; i < blk->count; i++) { in qup_i2c_xfer_v2_msg()
1439 blk->pos = i; in qup_i2c_xfer_v2_msg()
1440 blk->cur_tx_tags = blk->tags; in qup_i2c_xfer_v2_msg()
1441 blk->cur_blk_len = data_len; in qup_i2c_xfer_v2_msg()
1442 blk->tx_tag_len = in qup_i2c_xfer_v2_msg()
1443 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg); in qup_i2c_xfer_v2_msg()
1445 blk->cur_data = msg_buf; in qup_i2c_xfer_v2_msg()
1448 blk->total_tx_len = blk->tx_tag_len; in qup_i2c_xfer_v2_msg()
1449 blk->rx_tag_len = 2; in qup_i2c_xfer_v2_msg()
1450 blk->total_rx_len = blk->rx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1452 blk->total_tx_len = blk->tx_tag_len + data_len; in qup_i2c_xfer_v2_msg()
1453 blk->total_rx_len = 0; in qup_i2c_xfer_v2_msg()
1457 !qup->is_last || i < blk->count - 1); in qup_i2c_xfer_v2_msg()
1462 if (qup_i2c_check_msg_len(msg) && msg->len == 1 && in qup_i2c_xfer_v2_msg()
1463 !qup->is_smbus_read) { in qup_i2c_xfer_v2_msg()
1464 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX) in qup_i2c_xfer_v2_msg()
1465 return -EPROTO; in qup_i2c_xfer_v2_msg()
1467 msg->len = msg->buf[0]; in qup_i2c_xfer_v2_msg()
1468 qup->is_smbus_read = true; in qup_i2c_xfer_v2_msg()
1470 qup->is_smbus_read = false; in qup_i2c_xfer_v2_msg()
1474 msg->len += 1; in qup_i2c_xfer_v2_msg()
1478 blk->data_len -= qup->blk_xfer_limit; in qup_i2c_xfer_v2_msg()
1491 * This function determines the mode which will be used for this transfer. An
1492 * i2c transfer contains multiple message. Following are the rules to determine
1494 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1495 * 2. If complete transfer length is greater than fifo size then use the DMA
1523 if (!no_dma && qup->is_dma && in qup_i2c_determine_mode_v2()
1524 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) { in qup_i2c_determine_mode_v2()
1525 qup->use_dma = true; in qup_i2c_determine_mode_v2()
1527 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz - in qup_i2c_determine_mode_v2()
1529 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz - in qup_i2c_determine_mode_v2()
1543 qup->bus_err = 0; in qup_i2c_xfer_v2()
1544 qup->qup_err = 0; in qup_i2c_xfer_v2()
1546 ret = pm_runtime_get_sync(qup->dev); in qup_i2c_xfer_v2()
1554 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_xfer_v2()
1559 /* Configure QUP as I2C mini core */ in qup_i2c_xfer_v2()
1560 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG); in qup_i2c_xfer_v2()
1561 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN); in qup_i2c_xfer_v2()
1564 ret = -EIO; in qup_i2c_xfer_v2()
1568 if (qup->use_dma) { in qup_i2c_xfer_v2()
1569 reinit_completion(&qup->xfer); in qup_i2c_xfer_v2()
1571 qup->use_dma = false; in qup_i2c_xfer_v2()
1576 qup->msg = &msgs[idx]; in qup_i2c_xfer_v2()
1577 qup->is_last = idx == (num - 1); in qup_i2c_xfer_v2()
1584 qup->msg = NULL; in qup_i2c_xfer_v2()
1596 pm_runtime_mark_last_busy(qup->dev); in qup_i2c_xfer_v2()
1597 pm_runtime_put_autosuspend(qup->dev); in qup_i2c_xfer_v2()
1633 clk_prepare_enable(qup->clk); in qup_i2c_enable_clocks()
1634 clk_prepare_enable(qup->pclk); in qup_i2c_enable_clocks()
1642 clk_disable_unprepare(qup->clk); in qup_i2c_disable_clocks()
1643 config = readl(qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1645 writel(config, qup->base + QUP_CONFIG); in qup_i2c_disable_clocks()
1646 clk_disable_unprepare(qup->pclk); in qup_i2c_disable_clocks()
1667 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL); in qup_i2c_probe()
1669 return -ENOMEM; in qup_i2c_probe()
1671 qup->dev = &pdev->dev; in qup_i2c_probe()
1672 init_completion(&qup->xfer); in qup_i2c_probe()
1676 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq); in qup_i2c_probe()
1679 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq); in qup_i2c_probe()
1681 dev_notice(qup->dev, "using default clock-frequency %d", in qup_i2c_probe()
1686 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) { in qup_i2c_probe()
1687 qup->adap.algo = &qup_i2c_algo; in qup_i2c_probe()
1688 qup->adap.quirks = &qup_i2c_quirks; in qup_i2c_probe()
1691 qup->adap.algo = &qup_i2c_algo_v2; in qup_i2c_probe()
1692 qup->adap.quirks = &qup_i2c_quirks_v2; in qup_i2c_probe()
1694 if (acpi_match_device(qup_i2c_acpi_match, qup->dev)) in qup_i2c_probe()
1699 if (ret == -EPROBE_DEFER) in qup_i2c_probe()
1704 qup->max_xfer_sg_len = (MX_BLOCKS << 1); in qup_i2c_probe()
1706 qup->btx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1707 blocks, sizeof(*qup->btx.sg), in qup_i2c_probe()
1709 if (!qup->btx.sg) { in qup_i2c_probe()
1710 ret = -ENOMEM; in qup_i2c_probe()
1713 sg_init_table(qup->btx.sg, blocks); in qup_i2c_probe()
1715 qup->brx.sg = devm_kcalloc(&pdev->dev, in qup_i2c_probe()
1716 blocks, sizeof(*qup->brx.sg), in qup_i2c_probe()
1718 if (!qup->brx.sg) { in qup_i2c_probe()
1719 ret = -ENOMEM; in qup_i2c_probe()
1722 sg_init_table(qup->brx.sg, blocks); in qup_i2c_probe()
1727 qup->start_tag.start = devm_kzalloc(&pdev->dev, in qup_i2c_probe()
1729 if (!qup->start_tag.start) { in qup_i2c_probe()
1730 ret = -ENOMEM; in qup_i2c_probe()
1734 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1735 if (!qup->brx.tag.start) { in qup_i2c_probe()
1736 ret = -ENOMEM; in qup_i2c_probe()
1740 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL); in qup_i2c_probe()
1741 if (!qup->btx.tag.start) { in qup_i2c_probe()
1742 ret = -ENOMEM; in qup_i2c_probe()
1745 qup->is_dma = true; in qup_i2c_probe()
1751 dev_err(qup->dev, "clock frequency not supported %d\n", in qup_i2c_probe()
1753 ret = -EINVAL; in qup_i2c_probe()
1757 qup->base = devm_platform_ioremap_resource(pdev, 0); in qup_i2c_probe()
1758 if (IS_ERR(qup->base)) { in qup_i2c_probe()
1759 ret = PTR_ERR(qup->base); in qup_i2c_probe()
1763 qup->irq = platform_get_irq(pdev, 0); in qup_i2c_probe()
1764 if (qup->irq < 0) { in qup_i2c_probe()
1765 ret = qup->irq; in qup_i2c_probe()
1769 if (has_acpi_companion(qup->dev)) { in qup_i2c_probe()
1770 ret = device_property_read_u32(qup->dev, in qup_i2c_probe()
1771 "src-clock-hz", &src_clk_freq); in qup_i2c_probe()
1773 dev_notice(qup->dev, "using default src-clock-hz %d", in qup_i2c_probe()
1776 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev)); in qup_i2c_probe()
1778 qup->clk = devm_clk_get(qup->dev, "core"); in qup_i2c_probe()
1779 if (IS_ERR(qup->clk)) { in qup_i2c_probe()
1780 dev_err(qup->dev, "Could not get core clock\n"); in qup_i2c_probe()
1781 ret = PTR_ERR(qup->clk); in qup_i2c_probe()
1785 qup->pclk = devm_clk_get(qup->dev, "iface"); in qup_i2c_probe()
1786 if (IS_ERR(qup->pclk)) { in qup_i2c_probe()
1787 dev_err(qup->dev, "Could not get iface clock\n"); in qup_i2c_probe()
1788 ret = PTR_ERR(qup->pclk); in qup_i2c_probe()
1792 src_clk_freq = clk_get_rate(qup->clk); in qup_i2c_probe()
1799 writel(1, qup->base + QUP_SW_RESET); in qup_i2c_probe()
1804 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt, in qup_i2c_probe()
1808 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq); in qup_i2c_probe()
1812 hw_ver = readl(qup->base + QUP_HW_VERSION); in qup_i2c_probe()
1813 dev_dbg(qup->dev, "Revision %x\n", hw_ver); in qup_i2c_probe()
1815 io_mode = readl(qup->base + QUP_IO_MODE); in qup_i2c_probe()
1823 ret = -EIO; in qup_i2c_probe()
1826 qup->out_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1830 ret = -EIO; in qup_i2c_probe()
1833 qup->in_blk_sz = blk_sizes[size]; in qup_i2c_probe()
1838 * single transfer but the block size is in bytes so divide the in qup_i2c_probe()
1841 qup->in_blk_sz /= 2; in qup_i2c_probe()
1842 qup->out_blk_sz /= 2; in qup_i2c_probe()
1843 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1; in qup_i2c_probe()
1844 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1; in qup_i2c_probe()
1845 qup->write_rx_tags = qup_i2c_write_rx_tags_v1; in qup_i2c_probe()
1847 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2; in qup_i2c_probe()
1848 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2; in qup_i2c_probe()
1849 qup->write_rx_tags = qup_i2c_write_rx_tags_v2; in qup_i2c_probe()
1853 qup->out_fifo_sz = qup->out_blk_sz * (2 << size); in qup_i2c_probe()
1856 qup->in_fifo_sz = qup->in_blk_sz * (2 << size); in qup_i2c_probe()
1860 fs_div = ((src_clk_freq / clk_freq) / 2) - 3; in qup_i2c_probe()
1861 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1864 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3; in qup_i2c_probe()
1865 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff); in qup_i2c_probe()
1873 qup->one_byte_t = one_bit_t * 9; in qup_i2c_probe()
1874 qup->xfer_timeout = TOUT_MIN * HZ + in qup_i2c_probe()
1875 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t); in qup_i2c_probe()
1877 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n", in qup_i2c_probe()
1878 qup->in_blk_sz, qup->in_fifo_sz, in qup_i2c_probe()
1879 qup->out_blk_sz, qup->out_fifo_sz); in qup_i2c_probe()
1881 i2c_set_adapdata(&qup->adap, qup); in qup_i2c_probe()
1882 qup->adap.dev.parent = qup->dev; in qup_i2c_probe()
1883 qup->adap.dev.of_node = pdev->dev.of_node; in qup_i2c_probe()
1884 qup->is_last = true; in qup_i2c_probe()
1886 strscpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name)); in qup_i2c_probe()
1888 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC); in qup_i2c_probe()
1889 pm_runtime_use_autosuspend(qup->dev); in qup_i2c_probe()
1890 pm_runtime_set_active(qup->dev); in qup_i2c_probe()
1891 pm_runtime_enable(qup->dev); in qup_i2c_probe()
1893 ret = i2c_add_adapter(&qup->adap); in qup_i2c_probe()
1900 pm_runtime_disable(qup->dev); in qup_i2c_probe()
1901 pm_runtime_set_suspended(qup->dev); in qup_i2c_probe()
1905 if (qup->btx.dma) in qup_i2c_probe()
1906 dma_release_channel(qup->btx.dma); in qup_i2c_probe()
1907 if (qup->brx.dma) in qup_i2c_probe()
1908 dma_release_channel(qup->brx.dma); in qup_i2c_probe()
1916 if (qup->is_dma) { in qup_i2c_remove()
1917 dma_release_channel(qup->btx.dma); in qup_i2c_remove()
1918 dma_release_channel(qup->brx.dma); in qup_i2c_remove()
1921 disable_irq(qup->irq); in qup_i2c_remove()
1923 i2c_del_adapter(&qup->adap); in qup_i2c_remove()
1924 pm_runtime_disable(qup->dev); in qup_i2c_remove()
1925 pm_runtime_set_suspended(qup->dev); in qup_i2c_remove()
1968 { .compatible = "qcom,i2c-qup-v1.1.1" },
1969 { .compatible = "qcom,i2c-qup-v2.1.1" },
1970 { .compatible = "qcom,i2c-qup-v2.2.1" },
1988 MODULE_DESCRIPTION("Qualcomm QUP based I2C controller");