Lines Matching +full:i2c +full:- +full:transfer +full:- +full:timeout +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-exynos5.c - Samsung Exynos5 I2C Controller Driver
11 #include <linux/i2c.h>
33 * and for checking transfer status
205 /* Version of HS-I2C Hardware */
210 * struct exynos_hsi2c_variant - platform specific HSI2C driver data
212 * @hw: the hardware variant of Exynos I2C controller
245 .compatible = "samsung,exynos5-hsi2c",
248 .compatible = "samsung,exynos5250-hsi2c",
251 .compatible = "samsung,exynos5260-hsi2c",
254 .compatible = "samsung,exynos7-hsi2c",
257 .compatible = "samsung,exynosautov9-hsi2c",
263 static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c) in exynos5_i2c_clr_pend_irq() argument
265 writel(readl(i2c->regs + HSI2C_INT_STATUS), in exynos5_i2c_clr_pend_irq()
266 i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_clr_pend_irq()
276 * Returns 0 on success, -EINVAL if the cycle length cannot
279 static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings) in exynos5_i2c_set_timing() argument
291 unsigned int clkin = clk_get_rate(i2c->clk); in exynos5_i2c_set_timing()
292 unsigned int op_clk = hs_timings ? i2c->op_clock : in exynos5_i2c_set_timing()
293 (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) ? I2C_MAX_STANDARD_MODE_FREQ : in exynos5_i2c_set_timing()
294 i2c->op_clock; in exynos5_i2c_set_timing()
311 if (i2c->variant->hw == I2C_TYPE_EXYNOSAUTOV9) { in exynos5_i2c_set_timing()
312 div = ((clkin / (16 * i2c->op_clock)) - 1); in exynos5_i2c_set_timing()
315 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); in exynos5_i2c_set_timing()
317 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); in exynos5_i2c_set_timing()
337 * proportion factor for each I2C mode is used, which is calculated in exynos5_i2c_set_timing()
340 * ((t_low_min + (scl_clock - t_low_min - t_high_min) / 2) / scl_clock) in exynos5_i2c_set_timing()
343 * t_low_min is the minimal value of low period of the SCL clock in us; in exynos5_i2c_set_timing()
344 * t_high_min is the minimal value of high period of the SCL clock in us; in exynos5_i2c_set_timing()
345 * scl_clock is converted from SCL clock frequency into us. in exynos5_i2c_set_timing()
347 * Below are the proportion factors for these I2C modes: in exynos5_i2c_set_timing()
349 * Standard Mode: 4.7us, 4.0us, 10us, 0.535 in exynos5_i2c_set_timing()
350 * Fast Mode: 1.3us, 0.6us, 2.5us, 0.64 in exynos5_i2c_set_timing()
351 * Fast-Plus Mode: 0.5us, 0.26us, 1us, 0.62 in exynos5_i2c_set_timing()
354 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; in exynos5_i2c_set_timing()
355 temp = clkin / op_clk - 8 - t_ftl_cycle; in exynos5_i2c_set_timing()
356 if (i2c->variant->hw != I2C_TYPE_EXYNOS7) in exynos5_i2c_set_timing()
357 temp -= t_ftl_cycle; in exynos5_i2c_set_timing()
359 clk_cycle = temp / (div + 1) - 2; in exynos5_i2c_set_timing()
361 dev_err(i2c->dev, "%s clock set-up failed\n", in exynos5_i2c_set_timing()
363 return -EINVAL; in exynos5_i2c_set_timing()
367 * Scale clk_cycle to get t_scl_l using the proption factors for individual I2C modes. in exynos5_i2c_set_timing()
378 t_scl_h = clk_cycle - t_scl_l; in exynos5_i2c_set_timing()
391 dev_dbg(i2c->dev, "tSTART_SU: %X, tSTART_HD: %X, tSTOP_SU: %X\n", in exynos5_i2c_set_timing()
393 dev_dbg(i2c->dev, "tDATA_SU: %X, tSCL_L: %X, tSCL_H: %X\n", in exynos5_i2c_set_timing()
395 dev_dbg(i2c->dev, "nClkDiv: %X, tSR_RELEASE: %X\n", in exynos5_i2c_set_timing()
397 dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd); in exynos5_i2c_set_timing()
400 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); in exynos5_i2c_set_timing()
401 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); in exynos5_i2c_set_timing()
402 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); in exynos5_i2c_set_timing()
404 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); in exynos5_i2c_set_timing()
405 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); in exynos5_i2c_set_timing()
406 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); in exynos5_i2c_set_timing()
408 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); in exynos5_i2c_set_timing()
413 static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c) in exynos5_hsi2c_clock_setup() argument
416 int ret = exynos5_i2c_set_timing(i2c, false); in exynos5_hsi2c_clock_setup()
418 if (ret < 0 || i2c->op_clock < I2C_MAX_FAST_MODE_PLUS_FREQ) in exynos5_hsi2c_clock_setup()
421 return exynos5_i2c_set_timing(i2c, true); in exynos5_hsi2c_clock_setup()
425 * exynos5_i2c_init: configures the controller for I2C functionality
426 * Programs I2C controller for Master mode operation
428 static void exynos5_i2c_init(struct exynos5_i2c *i2c) in exynos5_i2c_init() argument
430 u32 i2c_conf = readl(i2c->regs + HSI2C_CONF); in exynos5_i2c_init()
431 u32 i2c_timeout = readl(i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init()
433 /* Clear to disable Timeout */ in exynos5_i2c_init()
435 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init()
438 i2c->regs + HSI2C_CTL); in exynos5_i2c_init()
439 writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL); in exynos5_i2c_init()
441 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) { in exynos5_i2c_init()
442 writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)), in exynos5_i2c_init()
443 i2c->regs + HSI2C_ADDR); in exynos5_i2c_init()
447 writel(i2c_conf | HSI2C_AUTO_MODE, i2c->regs + HSI2C_CONF); in exynos5_i2c_init()
450 static void exynos5_i2c_reset(struct exynos5_i2c *i2c) in exynos5_i2c_reset() argument
455 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
457 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
459 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
461 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_reset()
464 exynos5_hsi2c_clock_setup(i2c); in exynos5_i2c_reset()
466 exynos5_i2c_init(i2c); in exynos5_i2c_reset()
478 struct exynos5_i2c *i2c = dev_id; in exynos5_i2c_irq() local
483 i2c->state = -EINVAL; in exynos5_i2c_irq()
485 spin_lock(&i2c->lock); in exynos5_i2c_irq()
487 int_status = readl(i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_irq()
488 writel(int_status, i2c->regs + HSI2C_INT_STATUS); in exynos5_i2c_irq()
490 /* handle interrupt related to the transfer status */ in exynos5_i2c_irq()
491 switch (i2c->variant->hw) { in exynos5_i2c_irq()
496 i2c->trans_done = 1; in exynos5_i2c_irq()
497 i2c->state = 0; in exynos5_i2c_irq()
499 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); in exynos5_i2c_irq()
500 i2c->state = -EAGAIN; in exynos5_i2c_irq()
503 dev_dbg(i2c->dev, "No ACK from device\n"); in exynos5_i2c_irq()
504 i2c->state = -ENXIO; in exynos5_i2c_irq()
507 dev_dbg(i2c->dev, "No device\n"); in exynos5_i2c_irq()
508 i2c->state = -ENXIO; in exynos5_i2c_irq()
511 dev_dbg(i2c->dev, "Accessing device timed out\n"); in exynos5_i2c_irq()
512 i2c->state = -ETIMEDOUT; in exynos5_i2c_irq()
521 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_irq()
523 dev_dbg(i2c->dev, "No ACK from device\n"); in exynos5_i2c_irq()
524 i2c->state = -ENXIO; in exynos5_i2c_irq()
527 dev_dbg(i2c->dev, "No device\n"); in exynos5_i2c_irq()
528 i2c->state = -ENXIO; in exynos5_i2c_irq()
531 dev_dbg(i2c->dev, "Deal with arbitration lose\n"); in exynos5_i2c_irq()
532 i2c->state = -EAGAIN; in exynos5_i2c_irq()
535 dev_dbg(i2c->dev, "Accessing device timed out\n"); in exynos5_i2c_irq()
536 i2c->state = -ETIMEDOUT; in exynos5_i2c_irq()
539 i2c->trans_done = 1; in exynos5_i2c_irq()
540 i2c->state = 0; in exynos5_i2c_irq()
546 if ((i2c->msg->flags & I2C_M_RD) && (int_status & in exynos5_i2c_irq()
548 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); in exynos5_i2c_irq()
550 len = min(fifo_level, i2c->msg->len - i2c->msg_ptr); in exynos5_i2c_irq()
554 readl(i2c->regs + HSI2C_RX_DATA); in exynos5_i2c_irq()
555 i2c->msg->buf[i2c->msg_ptr++] = byte; in exynos5_i2c_irq()
556 len--; in exynos5_i2c_irq()
558 i2c->state = 0; in exynos5_i2c_irq()
560 fifo_status = readl(i2c->regs + HSI2C_FIFO_STATUS); in exynos5_i2c_irq()
563 len = i2c->variant->fifo_depth - fifo_level; in exynos5_i2c_irq()
564 if (len > (i2c->msg->len - i2c->msg_ptr)) { in exynos5_i2c_irq()
565 u32 int_en = readl(i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
568 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
569 len = i2c->msg->len - i2c->msg_ptr; in exynos5_i2c_irq()
573 byte = i2c->msg->buf[i2c->msg_ptr++]; in exynos5_i2c_irq()
574 writel(byte, i2c->regs + HSI2C_TX_DATA); in exynos5_i2c_irq()
575 len--; in exynos5_i2c_irq()
577 i2c->state = 0; in exynos5_i2c_irq()
581 if ((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || in exynos5_i2c_irq()
582 (i2c->state < 0)) { in exynos5_i2c_irq()
583 writel(0, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_irq()
584 exynos5_i2c_clr_pend_irq(i2c); in exynos5_i2c_irq()
585 complete(&i2c->msg_complete); in exynos5_i2c_irq()
588 spin_unlock(&i2c->lock); in exynos5_i2c_irq()
599 * Returns -EBUSY if the bus cannot be bought to idle
601 static int exynos5_i2c_wait_bus_idle(struct exynos5_i2c *i2c) in exynos5_i2c_wait_bus_idle() argument
609 trans_status = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_wait_bus_idle()
616 return -EBUSY; in exynos5_i2c_wait_bus_idle()
619 static void exynos5_i2c_bus_recover(struct exynos5_i2c *i2c) in exynos5_i2c_bus_recover() argument
623 val = readl(i2c->regs + HSI2C_CTL) | HSI2C_RXCHON; in exynos5_i2c_bus_recover()
624 writel(val, i2c->regs + HSI2C_CTL); in exynos5_i2c_bus_recover()
625 val = readl(i2c->regs + HSI2C_CONF) & ~HSI2C_AUTO_MODE; in exynos5_i2c_bus_recover()
626 writel(val, i2c->regs + HSI2C_CONF); in exynos5_i2c_bus_recover()
633 writel(HSI2C_CMD_READ_DATA, i2c->regs + HSI2C_MANUAL_CMD); in exynos5_i2c_bus_recover()
634 exynos5_i2c_wait_bus_idle(i2c); in exynos5_i2c_bus_recover()
635 writel(HSI2C_CMD_SEND_STOP, i2c->regs + HSI2C_MANUAL_CMD); in exynos5_i2c_bus_recover()
636 exynos5_i2c_wait_bus_idle(i2c); in exynos5_i2c_bus_recover()
638 val = readl(i2c->regs + HSI2C_CTL) & ~HSI2C_RXCHON; in exynos5_i2c_bus_recover()
639 writel(val, i2c->regs + HSI2C_CTL); in exynos5_i2c_bus_recover()
640 val = readl(i2c->regs + HSI2C_CONF) | HSI2C_AUTO_MODE; in exynos5_i2c_bus_recover()
641 writel(val, i2c->regs + HSI2C_CONF); in exynos5_i2c_bus_recover()
644 static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c) in exynos5_i2c_bus_check() argument
646 unsigned long timeout; in exynos5_i2c_bus_check() local
648 if (i2c->variant->hw == I2C_TYPE_EXYNOS5) in exynos5_i2c_bus_check()
656 timeout = jiffies + msecs_to_jiffies(100); in exynos5_i2c_bus_check()
658 u32 st = readl(i2c->regs + HSI2C_TRANS_STATUS); in exynos5_i2c_bus_check()
663 if (time_is_before_jiffies(timeout)) in exynos5_i2c_bus_check()
666 exynos5_i2c_bus_recover(i2c); in exynos5_i2c_bus_check()
672 * i2c: struct exynos5_i2c pointer for the current bus
673 * stop: Enables stop after transfer if set. Set for last transfer of
680 static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop) in exynos5_i2c_message_start() argument
690 if (i2c->variant->hw == I2C_TYPE_EXYNOS5) in exynos5_i2c_message_start()
695 i2c_ctl = readl(i2c->regs + HSI2C_CTL); in exynos5_i2c_message_start()
699 if (i2c->msg->flags & I2C_M_RD) { in exynos5_i2c_message_start()
704 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? in exynos5_i2c_message_start()
705 (i2c->variant->fifo_depth * 3 / 4) : i2c->msg->len; in exynos5_i2c_message_start()
713 trig_lvl = (i2c->msg->len > i2c->variant->fifo_depth) ? in exynos5_i2c_message_start()
714 (i2c->variant->fifo_depth * 1 / 4) : i2c->msg->len; in exynos5_i2c_message_start()
720 i2c_addr = HSI2C_SLV_ADDR_MAS(i2c->msg->addr); in exynos5_i2c_message_start()
722 if (i2c->op_clock >= I2C_MAX_FAST_MODE_PLUS_FREQ) in exynos5_i2c_message_start()
723 i2c_addr |= HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)); in exynos5_i2c_message_start()
725 writel(i2c_addr, i2c->regs + HSI2C_ADDR); in exynos5_i2c_message_start()
727 writel(fifo_ctl, i2c->regs + HSI2C_FIFO_CTL); in exynos5_i2c_message_start()
728 writel(i2c_ctl, i2c->regs + HSI2C_CTL); in exynos5_i2c_message_start()
730 exynos5_i2c_bus_check(i2c); in exynos5_i2c_message_start()
733 * Enable interrupts before starting the transfer so that we don't in exynos5_i2c_message_start()
736 spin_lock_irqsave(&i2c->lock, flags); in exynos5_i2c_message_start()
737 writel(int_en, i2c->regs + HSI2C_INT_ENABLE); in exynos5_i2c_message_start()
741 i2c_auto_conf |= i2c->msg->len; in exynos5_i2c_message_start()
743 writel(i2c_auto_conf, i2c->regs + HSI2C_AUTO_CONF); in exynos5_i2c_message_start()
744 spin_unlock_irqrestore(&i2c->lock, flags); in exynos5_i2c_message_start()
747 static bool exynos5_i2c_poll_irqs_timeout(struct exynos5_i2c *i2c, in exynos5_i2c_poll_irqs_timeout() argument
748 unsigned long timeout) in exynos5_i2c_poll_irqs_timeout() argument
750 unsigned long time_left = jiffies + timeout; in exynos5_i2c_poll_irqs_timeout()
753 !((i2c->trans_done && (i2c->msg->len == i2c->msg_ptr)) || in exynos5_i2c_poll_irqs_timeout()
754 (i2c->state < 0))) { in exynos5_i2c_poll_irqs_timeout()
755 while (readl(i2c->regs + HSI2C_INT_ENABLE) & in exynos5_i2c_poll_irqs_timeout()
756 readl(i2c->regs + HSI2C_INT_STATUS)) in exynos5_i2c_poll_irqs_timeout()
757 exynos5_i2c_irq(i2c->irq, i2c); in exynos5_i2c_poll_irqs_timeout()
763 static int exynos5_i2c_xfer_msg(struct exynos5_i2c *i2c, in exynos5_i2c_xfer_msg() argument
769 i2c->msg = msgs; in exynos5_i2c_xfer_msg()
770 i2c->msg_ptr = 0; in exynos5_i2c_xfer_msg()
771 i2c->trans_done = 0; in exynos5_i2c_xfer_msg()
773 reinit_completion(&i2c->msg_complete); in exynos5_i2c_xfer_msg()
775 exynos5_i2c_message_start(i2c, stop); in exynos5_i2c_xfer_msg()
777 if (!i2c->atomic) in exynos5_i2c_xfer_msg()
778 time_left = wait_for_completion_timeout(&i2c->msg_complete, in exynos5_i2c_xfer_msg()
781 time_left = exynos5_i2c_poll_irqs_timeout(i2c, in exynos5_i2c_xfer_msg()
785 ret = -ETIMEDOUT; in exynos5_i2c_xfer_msg()
787 ret = i2c->state; in exynos5_i2c_xfer_msg()
794 ret = exynos5_i2c_wait_bus_idle(i2c); in exynos5_i2c_xfer_msg()
797 exynos5_i2c_reset(i2c); in exynos5_i2c_xfer_msg()
798 if (ret == -ETIMEDOUT) in exynos5_i2c_xfer_msg()
799 dev_warn(i2c->dev, "%s timeout\n", in exynos5_i2c_xfer_msg()
800 (msgs->flags & I2C_M_RD) ? "rx" : "tx"); in exynos5_i2c_xfer_msg()
810 struct exynos5_i2c *i2c = adap->algo_data; in exynos5_i2c_xfer() local
813 ret = clk_enable(i2c->pclk); in exynos5_i2c_xfer()
817 ret = clk_enable(i2c->clk); in exynos5_i2c_xfer()
822 ret = exynos5_i2c_xfer_msg(i2c, msgs + i, i + 1 == num); in exynos5_i2c_xfer()
827 clk_disable(i2c->clk); in exynos5_i2c_xfer()
829 clk_disable(i2c->pclk); in exynos5_i2c_xfer()
837 struct exynos5_i2c *i2c = adap->algo_data; in exynos5_i2c_xfer_atomic() local
840 disable_irq(i2c->irq); in exynos5_i2c_xfer_atomic()
841 i2c->atomic = true; in exynos5_i2c_xfer_atomic()
843 i2c->atomic = false; in exynos5_i2c_xfer_atomic()
844 enable_irq(i2c->irq); in exynos5_i2c_xfer_atomic()
862 struct device_node *np = pdev->dev.of_node; in exynos5_i2c_probe()
863 struct exynos5_i2c *i2c; in exynos5_i2c_probe() local
866 i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL); in exynos5_i2c_probe()
867 if (!i2c) in exynos5_i2c_probe()
868 return -ENOMEM; in exynos5_i2c_probe()
870 if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock)) in exynos5_i2c_probe()
871 i2c->op_clock = I2C_MAX_STANDARD_MODE_FREQ; in exynos5_i2c_probe()
873 strscpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name)); in exynos5_i2c_probe()
874 i2c->adap.owner = THIS_MODULE; in exynos5_i2c_probe()
875 i2c->adap.algo = &exynos5_i2c_algorithm; in exynos5_i2c_probe()
876 i2c->adap.retries = 3; in exynos5_i2c_probe()
878 i2c->dev = &pdev->dev; in exynos5_i2c_probe()
879 i2c->clk = devm_clk_get(&pdev->dev, "hsi2c"); in exynos5_i2c_probe()
880 if (IS_ERR(i2c->clk)) { in exynos5_i2c_probe()
881 dev_err(&pdev->dev, "cannot get clock\n"); in exynos5_i2c_probe()
882 return -ENOENT; in exynos5_i2c_probe()
885 i2c->pclk = devm_clk_get_optional(&pdev->dev, "hsi2c_pclk"); in exynos5_i2c_probe()
886 if (IS_ERR(i2c->pclk)) { in exynos5_i2c_probe()
887 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->pclk), in exynos5_i2c_probe()
891 ret = clk_prepare_enable(i2c->pclk); in exynos5_i2c_probe()
895 ret = clk_prepare_enable(i2c->clk); in exynos5_i2c_probe()
899 i2c->regs = devm_platform_ioremap_resource(pdev, 0); in exynos5_i2c_probe()
900 if (IS_ERR(i2c->regs)) { in exynos5_i2c_probe()
901 ret = PTR_ERR(i2c->regs); in exynos5_i2c_probe()
905 i2c->adap.dev.of_node = np; in exynos5_i2c_probe()
906 i2c->adap.algo_data = i2c; in exynos5_i2c_probe()
907 i2c->adap.dev.parent = &pdev->dev; in exynos5_i2c_probe()
909 /* Clear pending interrupts from u-boot or misc causes */ in exynos5_i2c_probe()
910 exynos5_i2c_clr_pend_irq(i2c); in exynos5_i2c_probe()
912 spin_lock_init(&i2c->lock); in exynos5_i2c_probe()
913 init_completion(&i2c->msg_complete); in exynos5_i2c_probe()
915 i2c->irq = ret = platform_get_irq(pdev, 0); in exynos5_i2c_probe()
919 ret = devm_request_irq(&pdev->dev, i2c->irq, exynos5_i2c_irq, in exynos5_i2c_probe()
920 IRQF_NO_SUSPEND, dev_name(&pdev->dev), i2c); in exynos5_i2c_probe()
922 dev_err(&pdev->dev, "cannot request HS-I2C IRQ %d\n", i2c->irq); in exynos5_i2c_probe()
926 i2c->variant = of_device_get_match_data(&pdev->dev); in exynos5_i2c_probe()
928 ret = exynos5_hsi2c_clock_setup(i2c); in exynos5_i2c_probe()
932 exynos5_i2c_reset(i2c); in exynos5_i2c_probe()
934 ret = i2c_add_adapter(&i2c->adap); in exynos5_i2c_probe()
938 platform_set_drvdata(pdev, i2c); in exynos5_i2c_probe()
940 clk_disable(i2c->clk); in exynos5_i2c_probe()
941 clk_disable(i2c->pclk); in exynos5_i2c_probe()
946 clk_disable_unprepare(i2c->clk); in exynos5_i2c_probe()
949 clk_disable_unprepare(i2c->pclk); in exynos5_i2c_probe()
955 struct exynos5_i2c *i2c = platform_get_drvdata(pdev); in exynos5_i2c_remove() local
957 i2c_del_adapter(&i2c->adap); in exynos5_i2c_remove()
959 clk_unprepare(i2c->clk); in exynos5_i2c_remove()
960 clk_unprepare(i2c->pclk); in exynos5_i2c_remove()
965 struct exynos5_i2c *i2c = dev_get_drvdata(dev); in exynos5_i2c_suspend_noirq() local
967 i2c_mark_adapter_suspended(&i2c->adap); in exynos5_i2c_suspend_noirq()
968 clk_unprepare(i2c->clk); in exynos5_i2c_suspend_noirq()
969 clk_unprepare(i2c->pclk); in exynos5_i2c_suspend_noirq()
976 struct exynos5_i2c *i2c = dev_get_drvdata(dev); in exynos5_i2c_resume_noirq() local
979 ret = clk_prepare_enable(i2c->pclk); in exynos5_i2c_resume_noirq()
983 ret = clk_prepare_enable(i2c->clk); in exynos5_i2c_resume_noirq()
987 ret = exynos5_hsi2c_clock_setup(i2c); in exynos5_i2c_resume_noirq()
991 exynos5_i2c_init(i2c); in exynos5_i2c_resume_noirq()
992 clk_disable(i2c->clk); in exynos5_i2c_resume_noirq()
993 clk_disable(i2c->pclk); in exynos5_i2c_resume_noirq()
994 i2c_mark_adapter_resumed(&i2c->adap); in exynos5_i2c_resume_noirq()
999 clk_disable_unprepare(i2c->clk); in exynos5_i2c_resume_noirq()
1001 clk_disable_unprepare(i2c->pclk); in exynos5_i2c_resume_noirq()
1014 .name = "exynos5-hsi2c",
1022 MODULE_DESCRIPTION("Exynos5 HS-I2C Bus driver");