| /linux-6.12.1/include/dt-bindings/dma/ |
| D | dw-dmac.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
7 * Protection Control bits provide protection against illegal transactions.
8 * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
11 #define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */
12 #define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */
|
| /linux-6.12.1/Documentation/arch/x86/ |
| D | intel_txt.rst | 6 Technology (Intel(R) TXT), defines platform-level enhancements that
13 - Provides dynamic root of trust for measurement (DRTM)
14 - Data protection in case of improper shutdown
15 - Measurement and verification of launched environment
18 non-vPro systems. It is currently available on desktop systems
30 - LinuxTAG 2008:
31 http://www.linuxtag.org/2008/en/conf/events/vp-donnerstag.html
33 - TRUST2008:
34 http://www.trust-conference.eu/downloads/Keynote-Speakers/
35 3_David-Grawrock_The-Front-Door-of-Trusted-Computing.pdf
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| /linux-6.12.1/include/media/drv-intf/ |
| D | saa7146.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h> /* for delay-stuff */
7 #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
22 #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
23 #define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
67 dma_addr_t dma; member
107 u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
129 u32 revision; /* chip revision; needed for bug-workarounds*/
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-kernel-iommu_groups | 5 Description: /sys/kernel/iommu_groups/ contains a number of sub-
7 name of the sub-directory matches the iommu_group_id()
23 output direct-mapped, MSI, non mappable regions. Each
29 USB devices it is now exposed as "direct-relaxable" instead
43 DMA All the DMA transactions from the device in this group
45 DMA-FQ As above, but using batched invalidation to lazily
47 overhead at the cost of reduced memory protection.
48 identity All the DMA transactions from the device in this group
50 but zero protection.
56 - The device in the group is not bound to any device driver.
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| /linux-6.12.1/include/net/page_pool/ |
| D | types.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <linux/dma-direction.h>
11 #define PP_FLAG_DMA_MAP BIT(0) /* Should page_pool do the DMA
16 * DMA-synced-for-device according to
19 * Please note DMA-sync-for-CPU is still
40 * use-case. The NAPI budget is 64 packets. After a NAPI poll the RX
44 * Keeping room for more objects, is due to XDP_DROP use-case. As
46 * this array, as it shares the same softirq/NAPI protection. If
58 * struct page_pool_params - page pool parameters
63 * @dev: device, for DMA pre-mapping purposes
[all …]
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| /linux-6.12.1/kernel/configs/ |
| D | hardening.config | 3 # These are considered the basic kernel hardening, self-protection, and
34 # Basic stack frame overflow protection.
54 # Sampling-based heap out-of-bounds and use-after-free detection.
67 # https://trustedcomputinggroup.org/resource/pc-client-work-group-platform-reset-attack-mitigation-…
71 # Disable DMA between EFI hand-off and the kernel's IOMMU setup.
79 # Do not allow direct physical memory access to non-device memory.
90 # Enable Kernel Control Flow Integrity (currently Clang only).
|
| /linux-6.12.1/arch/m68k/include/asm/ |
| D | m5407sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
60 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
63 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
66 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
69 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
72 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
[all …]
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| D | m5307sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
62 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
64 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
66 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
68 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
70 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
[all …]
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| D | m5206sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
48 #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
57 #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
60 #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
70 #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
73 #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
76 #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
[all …]
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| D | m525xsim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
36 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
57 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
60 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
63 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
66 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
69 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
71 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
81 #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
[all …]
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| /linux-6.12.1/Documentation/admin-guide/sysctl/ |
| D | vm.rst | 13 ------------------------------------------------------------------------------
27 - admin_reserve_kbytes
28 - compact_memory
29 - compaction_proactiveness
30 - compact_unevictable_allowed
31 - dirty_background_bytes
32 - dirty_background_ratio
33 - dirty_bytes
34 - dirty_expire_centisecs
35 - dirty_ratio
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| /linux-6.12.1/drivers/net/ethernet/altera/ |
| D | altera_tse.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
116 u32 control; /* PHY device operation control register */ member
120 u32 auto_negotiation_advertisement; /* Auto-negotiation
168 /* The host processor uses this register to control and configure the
172 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
176 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
180 /* 14-bit maximum frame length. The MAC receive logic */
186 /* 12-bit receive FIFO section-empty threshold */
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| /linux-6.12.1/drivers/dma/dw/ |
| D | of.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Platform driver for the Synopsys DesignWare DMA Controller
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
19 struct dw_dma *dw = ofdma->of_dma_data; in dw_dma_of_xlate()
21 .dma_dev = dw->dma.dev, in dw_dma_of_xlate()
25 if (dma_spec->args_count < 3 || dma_spec->args_count > 4) in dw_dma_of_xlate()
28 slave.src_id = dma_spec->args[0]; in dw_dma_of_xlate()
29 slave.dst_id = dma_spec->args[0]; in dw_dma_of_xlate()
30 slave.m_master = dma_spec->args[1]; in dw_dma_of_xlate()
[all …]
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| /linux-6.12.1/include/linux/platform_data/ |
| D | dma-dw.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Driver for the Synopsys DesignWare DMA Controller
6 * Copyright (C) 2010-2011 ST Microelectronics
22 * struct dw_dma_slave - Controller-specific information about a slave
24 * @dma_dev: required DMA master device
43 * struct dw_dma_platform_data - Controller configuration parameters
54 * @protctl: Protection control signals setting per channel.
|
| /linux-6.12.1/Documentation/devicetree/bindings/dma/ |
| D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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|
| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| /linux-6.12.1/drivers/net/ethernet/cortina/ |
| D | gemini.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
46 /* TOE DMA Queue Size should be 2^n, n = 6...12
47 * TOE DMA Queues are the following queue types:
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
51 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
[all …]
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| /linux-6.12.1/Documentation/core-api/ |
| D | swiotlb.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 DMA and swiotlb
7 swiotlb is a memory buffer allocator used by the Linux kernel DMA layer. It is
8 typically used when a device doing DMA can't directly access the target memory
10 the DMA layer calls swiotlb to allocate a temporary memory buffer that conforms
11 to the limitations. The DMA is done to/from this temporary memory buffer, and
17 the DMA layer of the DMA attributes of the devices they are managing, and use
18 the normal DMA map, unmap, and sync APIs when programming a device to do DMA.
19 These APIs use the device DMA attributes and kernel-wide settings to determine
20 if bounce buffering is necessary. If so, the DMA layer manages the allocation,
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/mtd/ |
| D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
27 -- Additional SoC-specific NAND controller properties --
[all …]
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| /linux-6.12.1/Documentation/networking/device_drivers/ethernet/stmicro/ |
| D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
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| /linux-6.12.1/drivers/scsi/mvsas/ |
| D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
58 SPI_CTL = 0x10, /* EEPROM control */
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
127 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
[all …]
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| /linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
| D | main.h | 48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, ®s->regfoo);
55 * W_REG(osh, ®s->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
113 /* Interrupt bit error summary. Don't include I_RU: we refill DMA at other
145 ((uint)((wlc)->band->bandunit ? BAND_2G_INDEX : BAND_5G_INDEX))
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| /linux-6.12.1/drivers/comedi/drivers/ |
| D | s626.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
56 * Organization (physical order) and size (in DWORDs) of logical DMA buffers
60 * ADC DMA buffer must hold 16 samples,
64 * DAC output DMA buffer holds a single
68 /* All remaining space in 4KB DMA buffer is available for the RPS1 program. */
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| /linux-6.12.1/drivers/acpi/acpica/ |
| D | hwvalid.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
4 * Module Name: hwvalid - I/O request validation
6 * Copyright (C) 2000 - 2023, Intel Corp.
33 * DMA: DMA controller
37 * RTC: Real-time clock
39 * DMA1: DMA 1 page registers
40 * DMA1L: DMA 1 Ch 0 low page
41 * DMA2: DMA 2 page registers
42 * DMA2L: DMA 2 low page refresh
43 * ARBC: Arbitration control
[all …]
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| /linux-6.12.1/drivers/net/wireless/realtek/rtl8xxxu/ |
| D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
180 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
182 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
191 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */
197 control */
205 control */
212 control */
247 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
248 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */
[all …]
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