include/asm/m5206sim.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	m5206sim.h -- ColdFire 5206 System Integration Module support.
48 #define	MCFSIM_SYPCR		(MCF_MBAR + 0x41)	/* System Protection */
57 #define	MCFSIM_DCR0		(MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
60 #define	MCFSIM_DCR1		(MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
64 #define	MCFSIM_CSCR0		(MCF_MBAR + 0x6e)	/* CS 0 Control reg */
67 #define	MCFSIM_CSCR1		(MCF_MBAR + 0x7a)	/* CS 1 Control reg */
70 #define	MCFSIM_CSCR2		(MCF_MBAR + 0x86)	/* CS 2 Control reg */
73 #define	MCFSIM_CSCR3		(MCF_MBAR + 0x92)	/* CS 3 Control reg */
76 #define	MCFSIM_CSCR4		(MCF_MBAR + 0x9e)	/* CS 4 Control reg */
79 #define	MCFSIM_CSCR5		(MCF_MBAR + 0xaa)	/* CS 5 Control reg */
82 #define	MCFSIM_CSCR6		(MCF_MBAR + 0xb6)	/* CS 6 Control reg */
85 #define	MCFSIM_CSCR7		(MCF_MBAR + 0xc2)	/* CS 7 Control reg */
86 #define	MCFSIM_DMCR		(MCF_MBAR + 0xc6)	/* Default control */
100 #define	MCFDMA_BASE0		(MCF_MBAR + 0x200)	/* Base address DMA 0 */
101 #define	MCFDMA_BASE1		(MCF_MBAR + 0x240)	/* Base address DMA 1 */
124 #define MCFGPIO_IRQ_VECBASE	-1
125 #define MCFGPIO_IRQ_MAX		-1
138  *	Some symbol defines for the Interrupt Control Register
147 #define	MCFSIM_DMA1ICR		MCFSIM_ICR14	/* DMA 1 ICR */
148 #define	MCFSIM_DMA2ICR		MCFSIM_ICR15	/* DMA 2 ICR */