media/drv-intf/saa7146.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h>	/* for delay-stuff */
7 #include <linux/pci.h>		/* for pci-config-stuff, vendor ids etc. */
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
22 #define saa7146_write(sxy,adr,dat)    writel((dat),(sxy->mem+(adr)))
23 #define saa7146_read(sxy,adr)         readl(sxy->mem+(adr))
67 	dma_addr_t	dma;  member
107 	u32	irq_mask;	/* mask to indicate, which irq-events are handled by the extension */
129 	u32				revision;	/* chip revision; needed for bug-workarounds*/
131 	/* pci-device & irq stuff*/
146 	/* i2c-stuff */
184 #define SAA7146_I2C_TIMEOUT	100	/* i2c-timeout-value in ms */
185 #define SAA7146_I2C_RETRIES	3	/* how many times shall we retry an i2c-operation? */
186 #define SAA7146_I2C_DELAY	5	/* time we wait after certain i2c-operations */
234 #define GPIO3_MSK       0xFF000000  // GPIO #3 control bits
279 #define MASK_PR   0xfffffffe	/* Mask value for protection register */
285 #define BASE_ODD1         0x00  /* Video DMA 1 registers  */
289 #define BASE_PAGE1        0x10  /* Video DMA 1 base page */
292 #define BASE_ODD2         0x18  /* Video DMA 2 registers */
296 #define BASE_PAGE2        0x28  /* Video DMA 2 base page */
299 #define BASE_ODD3         0x30  /* Video DMA 3 registers */
303 #define BASE_PAGE3        0x40  /* Video DMA 3 base page */
317 #define BRS_CTRL          0x58  /* BRS control register */
318 #define HPS_CTRL          0x5C  /* HPS control register */
323 #define BCS_CTRL          0x70  /* BCS control */
335 #define BASE_A1_IN        0x94	/* Audio 1 input DMA */
339 #define BASE_A1_OUT       0xA0  /* Audio 1 output DMA */
343 #define BASE_A2_IN        0xAC  /* Audio 2 input DMA */
347 #define BASE_A2_OUT       0xB8  /* Audio 2 output DMA */
362 #define GPIO_CTRL         0xE0  /* GPIO 0-3 register */
372 #define MC1               0xFC   /* Main control register 1 */
373 #define MC2               0x100  /* Main control register 2  */
385 #define PCI_VDP1          0x120  /* Video DMA pointer of FIFO 1 */
386 #define PCI_VDP2          0x124  /* Video DMA pointer of FIFO 2 */
387 #define PCI_VDP3          0x128  /* Video DMA pointer of FIFO 3 */
388 #define PCI_ADP1          0x12C  /* Audio DMA pointer of audio out 1 */
389 #define PCI_ADP2          0x130  /* Audio DMA pointer of audio in 1 */
390 #define PCI_ADP3          0x134  /* Audio DMA pointer of audio out 2 */
391 #define PCI_ADP4          0x138  /* Audio DMA pointer of audio in 2 */
392 #define PCI_DMA_DDP       0x13C  /* DEBI DMA pointer */
395 #define A_TIME_SLOT1      0x180,  /* from 180 - 1BC */
396 #define A_TIME_SLOT2      0x1C0,  /* from 1C0 - 1FC */
415 #define SPCI_A2_IN      0x00008000  /* Audio 2 input DMA protection / limit */
416 #define SPCI_A2_OUT     0x00004000  /* Audio 2 output DMA protection / limit */
417 #define SPCI_A1_IN      0x00002000  /* Audio 1 input DMA protection / limit */
418 #define SPCI_A1_OUT     0x00001000  /* Audio 1 output DMA protection / limit */
419 #define SPCI_AFOU       0x00000800  /* Audio FIFO over- / underflow */
420 #define SPCI_V_PE       0x00000400  /* Video protection address */
421 #define SPCI_VFOU       0x00000200  /* Video FIFO over- / underflow */
459 	spin_lock_irqsave(&x->int_slock, flags);  in SAA7146_IER_DISABLE()
461 	spin_unlock_irqrestore(&x->int_slock, flags);  in SAA7146_IER_DISABLE()
467 	spin_lock_irqsave(&x->int_slock, flags);  in SAA7146_IER_ENABLE()
469 	spin_unlock_irqrestore(&x->int_slock, flags);  in SAA7146_IER_ENABLE()