include/asm/m5407sim.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	m5407sim.h -- ColdFire 5407 System Integration Module support.
28 #define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
53 #define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
56 #define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */
60 #define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
63 #define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
66 #define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
69 #define MCFSIM_CSCR5		(MCF_MBAR + 0xc6)	/* CS 5 Control reg */
72 #define MCFSIM_CSCR6		(MCF_MBAR + 0xd2)	/* CS 6 Control reg */
75 #define MCFSIM_CSCR7		(MCF_MBAR + 0xde)	/* CS 7 Control reg */
77 #define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
96  *	DMA unit base addresses.
98 #define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
99 #define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
100 #define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
101 #define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
107 #define MCFGPIO_IRQ_MAX		-1
108 #define MCFGPIO_IRQ_VECBASE	-1
119 #define	MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
120 #define	MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
121 #define	MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
122 #define	MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */