scsi/mvsas/mv_defs.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
7  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 	MVS_TX_RING_SZ		= 1024,	/* TX ring size (12-bit) */
31 	MVS_RX_RING_SZ		= 1024, /* RX ring size (12-bit) */
32 					/* software requires power-of-2
44 	MVS_SOC_CAN_QUEUE	= MVS_SOC_SLOTS - 2,
58 	SPI_CTL			= 0x10,	/* EEPROM control */
79 	/* MVS_GBL_PORT_TYPE */			/* shl for ports 1-3 */
127 	CINT_DMA_PCIE		= (1U << 27),	/* DMA to PCIE timeout */
135 						/* shl for ports 1-3 */
173 	MCH_PRD_LEN_SHIFT	= 16,		/* 16-bit PRD table len */
190 	MCH_PASSTHRU		= (1U << 12),	/* pass-through (SSP) */
194 	MCH_PROTECTION		= (1U << 8),	/* protection info rec (SSP) */
196 	MCH_FPDMA		= (1U << 6),	/* First party DMA (STP/SATA) */
209 	/* MVS_Px_SER_CTLSTAT (per-phy control) */
216 	/* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
224 	PHYEV_POOF		= (1U << 12),	/* phy ready from 1 -> 0 */
245 	PCS_SELF_CLEAR		= (1U << 5),	/* self-clearing int mode */
247 	PCS_CMD_STOP_ERR	= (1U << 3),	/* cmd stop-on-err enable */
296 	PHYR_SATA_CTL		= 0x18,	/* SATA control */
298 	PHYR_SATA_SIG0	= 0x20,	/*port SATA signature FIS(Byte 0-3) */
299 	PHYR_SATA_SIG1	= 0x24,	/*port SATA signature FIS(Byte 4-7) */
300 	PHYR_SATA_SIG2	= 0x28,	/*port SATA signature FIS(Byte 8-11) */
301 	PHYR_SATA_SIG3	= 0x2c,	/*port SATA signature FIS(Byte 12-15) */
329 	CMD_OOB_SPACE	= 0x110, /* OOB space control register */
330 	CMD_OOB_BURST	= 0x114, /* OOB burst control register */
331 	CMD_PHY_TIMER		= 0x118, /* PHY timer control register */
334 	CMD_SAS_CTL0		= 0x124, /* SAS control register 0 */
335 	CMD_SAS_CTL1		= 0x128, /* SAS control register 1 */
336 	CMD_SAS_CTL2		= 0x12c, /* SAS control register 2 */
337 	CMD_SAS_CTL3		= 0x130, /* SAS control register 3 */
342 	CMD_APP_MEM_CTL	= 0x144, /* Application Memory Control */
343 	CMD_XOR_MEM_CTL	= 0x148, /* XOR Block Memory Control */
344 	CMD_DMA_MEM_CTL	= 0x14c, /* DMA Block Memory Control */
345 	CMD_PORT_MEM_CTL0	= 0x150, /* Port Memory Control 0 */
346 	CMD_PORT_MEM_CTL1	= 0x154, /* Port Memory Control 1 */
347 	CMD_SATA_PORT_MEM_CTL0	= 0x158, /* SATA Port Memory Control 0 */
348 	CMD_SATA_PORT_MEM_CTL1	= 0x15c, /* SATA Port Memory Control 1 */
349 	CMD_XOR_MEM_BIST_CTL	= 0x160, /* XOR Memory BIST Control */
351 	CMD_DMA_MEM_BIST_CTL	= 0x168, /* DMA Memory BIST Control */
352 	CMD_DMA_MEM_BIST_STAT	= 0x16c, /* DMA Memory BIST Status */
353 	CMD_PORT_MEM_BIST_CTL	= 0x170, /* Port Memory BIST Control */
356 	CMD_STP_MEM_BIST_CTL	= 0x17c, /* STP Memory BIST Control */
362 	CMD_PHY_CTL		= 0x194, /* PHY Control and Status */
367 	CMD_PND_FIFO_CTL0	= 0x1A8, /* Pending FIFO Control 0 */
368 	CMD_HOST_CTL		= 0x1AC, /* Host Control Status */
374 	CMD_PND_FIFO_CTL1	= 0x1C4, /* Pending FIFO Control 1 */
424 	CMD_PI_ERR	= (1U << 30),	/* Protection info error.  see flags2 */
428 	DMA_TERM	= (1U << 26),	/* DMA terminate primitive rx'd */