Lines Matching +full:dma +full:- +full:protection +full:- +full:control
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
180 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
182 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
191 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */
197 control */
205 control */
212 control */
247 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
248 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */
251 #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt
263 #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */
264 #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */
265 #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */
266 #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */
267 #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */
268 #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */
270 #define IMR0_ROK BIT(0) /* Receive DMA OK */
273 #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
274 #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
275 #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
276 #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
277 #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
278 #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
279 #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
280 #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */
281 #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */
282 #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */
283 #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */
284 #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */
285 #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */
286 #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */
299 /* Efuse access protection for RTL8723 */
342 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */
502 #define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits
503 8-14: USB DMA timeout
761 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use
765 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
772 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection
859 #define REG_RXFLTMAP1 0x06a2 /* Control frames */
1233 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK
1235 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK
1237 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */
1238 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */
1239 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */
1240 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */
1243 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
1257 #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */
1258 #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */
1260 #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */
1266 #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */
1269 #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */
1270 #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */
1289 * 0-7 have the same meaning.
1352 #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */
1353 #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */
1354 #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */
1355 #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */
1356 #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */
1357 #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */
1358 #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */
1359 #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */
1361 #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */
1363 #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */
1364 #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */
1365 #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */