include/asm/m525xsim.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	m525xsim.h -- ColdFire 525x System Integration Module support.
36 #define MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */
57 #define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */
60 #define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */
63 #define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */
66 #define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */
69 #define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */
71 #define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */
81 #define MCFINTC2_INTPRI1	(MCF_MBAR2 + 0x140)	/* 0-7 priority */
82 #define MCFINTC2_INTPRI2	(MCF_MBAR2 + 0x144)	/* 8-15 priority */
83 #define MCFINTC2_INTPRI3	(MCF_MBAR2 + 0x148)	/* 16-23 priority */
84 #define MCFINTC2_INTPRI4	(MCF_MBAR2 + 0x14c)	/* 24-31 priority */
85 #define MCFINTC2_INTPRI5	(MCF_MBAR2 + 0x150)	/* 32-39 priority */
86 #define MCFINTC2_INTPRI6	(MCF_MBAR2 + 0x154)	/* 40-47 priority */
87 #define MCFINTC2_INTPRI7	(MCF_MBAR2 + 0x158)	/* 48-55 priority */
88 #define MCFINTC2_INTPRI8	(MCF_MBAR2 + 0x15c)	/* 56-63 priority */
91 				((((i) - MCFINTC2_VECBASE) / 8) * 4))
134  *	DMA unit base addresses.
136 #define MCFDMA_BASE0		(MCF_MBAR + 0x300)	/* Base address DMA 0 */
137 #define MCFDMA_BASE1		(MCF_MBAR + 0x340)	/* Base address DMA 1 */
138 #define MCFDMA_BASE2		(MCF_MBAR + 0x380)	/* Base address DMA 2 */
139 #define MCFDMA_BASE3		(MCF_MBAR + 0x3C0)	/* Base address DMA 3 */
150 #define MCFSIM_DMA0ICR		MCFSIM_ICR6	/* DMA 0 ICR */
151 #define MCFSIM_DMA1ICR		MCFSIM_ICR7	/* DMA 1 ICR */
152 #define MCFSIM_DMA2ICR		MCFSIM_ICR8	/* DMA 2 ICR */
153 #define MCFSIM_DMA3ICR		MCFSIM_ICR9	/* DMA 3 ICR */
202 #define MCFSIM2_DMAROUTE	(MCF_MBAR2 + 0x188)     /* DMA routing */
211 #define MCFGPIO_IRQ_MAX		-1
212 #define MCFGPIO_IRQ_VECBASE	-1
264 	 *	PLL for 140MHz. Lets go fast :-)
301         orl	%d0,0x4(%a1)			/* de-assert IDE reset */