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/linux-6.12.1/arch/mips/kernel/
Dcevt-bcm1480.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
34 void __iomem *cfg, *init; in sibyte_set_periodic() local
36 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
37 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
39 __raw_writeq(0, cfg); in sibyte_set_periodic()
40 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
41 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, cfg); in sibyte_set_periodic()
47 unsigned int cpu = smp_processor_id(); in sibyte_shutdown() local
48 void __iomem *cfg; in sibyte_shutdown() local
[all …]
Dcevt-sb1250.c1 // SPDX-License-Identifier: GPL-2.0-or-later
31 void __iomem *cfg; in sibyte_shutdown() local
33 cfg = IOADDR(A_SCD_TIMER_REGISTER(smp_processor_id(), R_SCD_TIMER_CFG)); in sibyte_shutdown()
36 __raw_writeq(0, cfg); in sibyte_shutdown()
43 unsigned int cpu = smp_processor_id(); in sibyte_set_periodic() local
44 void __iomem *cfg, *init; in sibyte_set_periodic() local
46 cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)); in sibyte_set_periodic()
47 init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)); in sibyte_set_periodic()
49 __raw_writeq(0, cfg); in sibyte_set_periodic()
50 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, init); in sibyte_set_periodic()
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Dsmp-bmips.c20 #include <linux/cpu.h>
40 #include <asm/cpu-features.h>
53 static void bmips_set_reset_vec(int cpu, u32 val);
59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
63 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
64 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
72 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift)) argument
73 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
74 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8)) argument
75 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0)) argument
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Dcpu-r3k-probe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 1994 - 2006 Ralf Baechle
18 #include <asm/cpu.h>
19 #include <asm/cpu-features.h>
20 #include <asm/cpu-type.h>
26 #include "fpu-probe.h"
38 * Probe whether cpu has config register by trying to play with
46 unsigned long cfg = read_c0_conf(); in cpu_has_confreg() local
49 write_c0_conf(cfg ^ R30XX_CONF_AC); in cpu_has_confreg()
51 write_c0_conf(cfg); in cpu_has_confreg()
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/linux-6.12.1/arch/arm/mach-omap2/
Domap-smp.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
52 static struct omap_smp_config cfg; variable
71 return cfg.scu_base; in omap4_get_scu_base()
87 * BIT(27) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
89 * BIT(25) - Disables streaming. All write-allocate lines allocate in in omap5_erratum_workaround_801819()
100 pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n", in omap5_erratum_workaround_801819()
139 pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n", in omap5_secondary_harden_predictor()
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/linux-6.12.1/arch/x86/kernel/apic/
Dmsi.c1 // SPDX-License-Identifier: GPL-2.0-only
26 static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg) in irq_msi_update_msg() argument
30 __irq_msi_compose_msg(cfg, msg, false); in irq_msi_update_msg()
31 irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg); in irq_msi_update_msg()
37 struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd); in msi_set_affinity() local
38 struct irq_data *parent = irqd->parent_data; in msi_set_affinity()
39 unsigned int cpu; in msi_set_affinity() local
43 cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd)); in msi_set_affinity()
44 old_cfg = *cfg; in msi_set_affinity()
47 ret = parent->chip->irq_set_affinity(parent, mask, force); in msi_set_affinity()
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/linux-6.12.1/arch/mips/loongson64/
Dhpet.c1 // SPDX-License-Identifier: GPL-2.0
35 unsigned int cfg = smbus_read(offset); in smbus_enable() local
37 cfg |= bit; in smbus_enable()
38 smbus_write(offset, cfg); in smbus_enable()
53 unsigned int cfg = hpet_read(HPET_CFG); in hpet_start_counter() local
55 cfg |= HPET_CFG_ENABLE; in hpet_start_counter()
56 hpet_write(HPET_CFG, cfg); in hpet_start_counter()
61 unsigned int cfg = hpet_read(HPET_CFG); in hpet_stop_counter() local
63 cfg &= ~HPET_CFG_ENABLE; in hpet_stop_counter()
64 hpet_write(HPET_CFG, cfg); in hpet_stop_counter()
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/linux-6.12.1/arch/x86/kernel/
Dhpet.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/cpu.h>
28 unsigned int cpu; member
133 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
143 u32 i, id, period, cfg, status, channels, l, h; in _hpet_print_config() local
151 cfg = hpet_readl(HPET_CFG); in _hpet_print_config()
153 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status); in _hpet_print_config()
210 hd.hd_irq[i] = hc->irq; in hpet_reserve_platform_timers()
212 switch (hc->mode) { in hpet_reserve_platform_timers()
215 hc->mode = HPET_MODE_DEVICE; in hpet_reserve_platform_timers()
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/linux-6.12.1/drivers/tty/
Dmips_ejtag_fdc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2007-2015 Imagination Technologies Ltd
87 * struct mips_ejtag_fdc_tty_port - Wrapper struct for FDC tty_port.
117 * struct mips_ejtag_fdc_tty - Driver data for FDC as a whole.
120 * @cpu: CPU number for this FDC.
123 * @ports: Per-channel data.
144 unsigned int cpu; member
174 __raw_writel(data, priv->reg + offs); in mips_ejtag_fdc_write()
180 return __raw_readl(priv->reg + offs); in mips_ejtag_fdc_read()
186 * struct fdc_word - FDC word encoding some number of bytes of data.
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/linux-6.12.1/arch/arm/mach-s3c/
Dinit.c1 // SPDX-License-Identifier: GPL-2.0
7 // S3C series CPU initialisation
26 #include "cpu.h"
29 static struct cpu_table *cpu; variable
35 for (; count != 0; count--, tab++) { in s3c_lookup_cpu()
36 if ((idcode & tab->idmask) == (tab->idcode & tab->idmask)) in s3c_lookup_cpu()
46 cpu = s3c_lookup_cpu(idcode, cputab, cputab_size); in s3c_init_cpu()
48 if (cpu == NULL) { in s3c_init_cpu()
49 printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode); in s3c_init_cpu()
50 panic("Unknown S3C24XX CPU"); in s3c_init_cpu()
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/linux-6.12.1/tools/testing/selftests/bpf/map_tests/
Dtask_storage_map.c1 // SPDX-License-Identifier: GPL-2.0
33 while (!ctx->start) in lookup_fn()
36 while (!ctx->stop && i++ < ctx->loop) in lookup_fn()
37 bpf_map_lookup_elem(ctx->map_fd, &ctx->pid_fd, &value); in lookup_fn()
45 ctx->stop = true; in abort_lookup()
46 ctx->start = true; in abort_lookup()
54 unsigned int i, nr = 256, loop = 8192, cpu = 0; in test_task_storage_map_stress_lookup() local
59 const char *cfg; in test_task_storage_map_stress_lookup() local
62 cfg = getenv("TASK_STORAGE_MAP_NR_THREAD"); in test_task_storage_map_stress_lookup()
63 if (cfg) { in test_task_storage_map_stress_lookup()
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/linux-6.12.1/drivers/irqchip/
Dirq-ls-scfg-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale SCFG MSI(-X) support
53 struct ls_scfg_msi_cfg *cfg; member
77 if (p && strncmp(p, "no-affinity", 11) == 0) in early_parse_ls_scfg_msi()
90 msg->address_hi = upper_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
91 msg->address_lo = lower_32_bits(msi_data->msiir_addr); in ls_scfg_msi_compose_msg()
92 msg->data = data->hwirq; in ls_scfg_msi_compose_msg()
98 msg->data |= cpumask_first(mask); in ls_scfg_msi_compose_msg()
108 u32 cpu; in ls_scfg_msi_set_affinity() local
111 return -EINVAL; in ls_scfg_msi_set_affinity()
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/linux-6.12.1/arch/arm/mach-imx/
Dmmdc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
76 { .compatible = "fsl,imx6q-mmdc", .data = (void *)&imx6q_data},
77 { .compatible = "fsl,imx6qp-mmdc", .data = (void *)&imx6qp_data},
86 PMU_EVENT_ATTR_STRING(total-cycles, mmdc_pmu_total_cycles, "event=0x00")
87 PMU_EVENT_ATTR_STRING(busy-cycles, mmdc_pmu_busy_cycles, "event=0x01")
88 PMU_EVENT_ATTR_STRING(read-accesses, mmdc_pmu_read_accesses, "event=0x02")
89 PMU_EVENT_ATTR_STRING(write-accesses, mmdc_pmu_write_accesses, "event=0x03")
90 PMU_EVENT_ATTR_STRING(read-bytes, mmdc_pmu_read_bytes, "event=0x04")
91 PMU_EVENT_ATTR_STRING(read-bytes.unit, mmdc_pmu_read_bytes_unit, "MB");
92 PMU_EVENT_ATTR_STRING(read-bytes.scale, mmdc_pmu_read_bytes_scale, "0.000001");
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/linux-6.12.1/drivers/clk/samsung/
Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * This file contains the utility function to register CPU clock for Samsung
10 * Exynos platforms. A CPU clock is defined as a clock supplied to a CPU or a
11 * group of CPUs. The CPU clock is typically derived from a hierarchy of clock
13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
15 * CPU clock rate and this relation is usually specified in the hardware manual
18 * The below implementation of the CPU clock allows the rate changes of the CPU
19 * clock and the corresponding rate changes of the auxiliary clocks of the CPU
22 * registers to achieve a fast coordinated rate change for all the CPU domain
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/linux-6.12.1/arch/riscv/kvm/
Dvcpu.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/entry-kvm.h>
51 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_reset_vcpu()
52 struct kvm_vcpu_csr *reset_csr = &vcpu->arch.guest_reset_csr; in kvm_riscv_reset_vcpu()
53 struct kvm_cpu_context *cntx = &vcpu->arch.guest_context; in kvm_riscv_reset_vcpu()
54 struct kvm_cpu_context *reset_cntx = &vcpu->arch.guest_reset_context; in kvm_riscv_reset_vcpu()
63 loaded = (vcpu->cpu != -1); in kvm_riscv_reset_vcpu()
67 vcpu->arch.last_exit_cpu = -1; in kvm_riscv_reset_vcpu()
71 spin_lock(&vcpu->arch.reset_cntx_lock); in kvm_riscv_reset_vcpu()
73 spin_unlock(&vcpu->arch.reset_cntx_lock); in kvm_riscv_reset_vcpu()
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/linux-6.12.1/drivers/iommu/
Dhyperv-iommu.c1 // SPDX-License-Identifier: GPL-2.0
4 * Hyper-V stub IOMMU driver.
18 #include <asm/cpu.h>
30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
42 struct irq_data *parent = data->parent_data; in hyperv_ir_set_affinity()
43 struct irq_cfg *cfg = irqd_cfg(data); in hyperv_ir_set_affinity() local
48 return -EINVAL; in hyperv_ir_set_affinity()
50 ret = parent->chip->irq_set_affinity(parent, mask, force); in hyperv_ir_set_affinity()
54 vector_schedule_cleanup(cfg); in hyperv_ir_set_affinity()
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/linux-6.12.1/include/linux/perf/
Darm_pmu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * The Armv7 and Armv8.8 or less CPU PMU supports up to 32 event counters.
21 * The Armv8.9/9.4 CPU PMU supports up to 33 event counters.
44 [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
47 [0 ... C(MAX) - 1] = { \
48 [0 ... C(OP_MAX) - 1] = { \
49 [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED, \
68 * already have to allocate this struct per cpu.
104 bool secure_access; /* 32-bit ARM only */
113 /* the attr_groups array must be NULL-terminated */
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/linux-6.12.1/arch/x86/platform/uv/
Duv_irq.c27 static void uv_program_mmr(struct irq_cfg *cfg, struct uv_irq_2_mmr_pnode *info) in uv_program_mmr() argument
37 entry->vector = cfg->vector; in uv_program_mmr()
38 entry->delivery_mode = APIC_DELIVERY_MODE_FIXED; in uv_program_mmr()
39 entry->dest_mode = apic->dest_mode_logical; in uv_program_mmr()
40 entry->polarity = 0; in uv_program_mmr()
41 entry->trigger = 0; in uv_program_mmr()
42 entry->mask = 0; in uv_program_mmr()
43 entry->dest = cfg->dest_apicid; in uv_program_mmr()
45 uv_write_global_mmr64(info->pnode, info->offset, mmr_value); in uv_program_mmr()
54 struct irq_data *parent = data->parent_data; in uv_set_irq_affinity()
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/linux-6.12.1/arch/x86/events/
Drapl.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Intel RAPL interface is specified in the IA-32 Manual Vol3b
34 * gpu counter: consumption of the builtin-gpu domain (client only)
38 * psys counter: consumption of the builtin-psys domain (client only)
42 * We manage those counters as free running (read-only). They may be
45 * The events only support system-wide mode counting. There is no
49 * Because we want to avoid floating-point operations in the kernel,
53 * ldexp(raw_count, -32);
63 #include <asm/intel-family.h>
85 "pp0-core",
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/linux-6.12.1/arch/x86/kernel/cpu/resctrl/
Dctrlmondata.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * - Cache Allocation code.
18 #include <linux/cpu.h>
40 if (!r->membw.delay_linear && r->membw.arch_needs_linear) { in bw_validate()
41 rdt_last_cmd_puts("No support for non-linear MB domains\n"); in bw_validate()
57 if (bw < r->membw.min_bw || bw > r->default_ctrl) { in bw_validate()
59 bw, r->membw.min_bw, r->default_ctrl); in bw_validate()
63 *data = roundup(bw, (unsigned long)r->membw.bw_gran); in bw_validate()
70 struct resctrl_staged_config *cfg; in parse_bw() local
71 u32 closid = data->rdtgrp->closid; in parse_bw()
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/linux-6.12.1/arch/x86/pci/
Dmmconfig_32.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
29 struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); in get_base_addr() local
31 if (cfg) in get_base_addr()
32 return cfg->address; in get_base_addr()
42 int cpu = smp_processor_id(); in pci_exp_set_dev_base() local
44 cpu != mmcfg_last_accessed_cpu) { in pci_exp_set_dev_base()
46 mmcfg_last_accessed_cpu = cpu; in pci_exp_set_dev_base()
58 err: *value = -1; in pci_mmcfg_read()
59 return -EINVAL; in pci_mmcfg_read()
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/linux-6.12.1/drivers/perf/
Dcxl_pmu.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/io-64-nonatomic-lo-hi.h>
66 /* CXL rev 3.0 Table 13-5 Events under CXL Vendor ID */
120 * - Fixed function counters refer to an Event Capabilities register.
127 void __iomem *base = info->base; in cxl_pmu_parse_caps()
137 return -ENODEV; in cxl_pmu_parse_caps()
140 info->num_counters = FIELD_GET(CXL_PMU_CAP_NUM_COUNTERS_MSK, val) + 1; in cxl_pmu_parse_caps()
141 info->counter_width = FIELD_GET(CXL_PMU_CAP_COUNTER_WIDTH_MSK, val); in cxl_pmu_parse_caps()
142 info->num_event_capabilities = FIELD_GET(CXL_PMU_CAP_NUM_EVN_CAP_REG_SUP_MSK, val) + 1; in cxl_pmu_parse_caps()
144 info->filter_hdm = FIELD_GET(CXL_PMU_CAP_FILTERS_SUP_MSK, val) & CXL_PMU_FILTER_HDM; in cxl_pmu_parse_caps()
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/linux-6.12.1/arch/x86/kernel/cpu/mce/
Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <linux/cpu.h>
87 .bootlog = -1,
88 .monarch_timeout = -1
99 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
115 * CPU/chipset specific EDAC code can register a notifier call here to print
116 * MCE errors in a human-readable form.
124 m->cpuid = cpuid_eax(1); in mce_prep_record_common()
125 m->cpuvendor = boot_cpu_data.x86_vendor; in mce_prep_record_common()
126 m->mcgcap = __rdmsr(MSR_IA32_MCG_CAP); in mce_prep_record_common()
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/linux-6.12.1/drivers/media/pci/intel/ipu6/
Dipu6-fw-com.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013--2024 Intel Corporation
7 #include <linux/dma-mapping.h>
14 #include "ipu6-bus.h"
15 #include "ipu6-fw-com.h"
22 * system RAM and are mapped to ISP MMU so that both CPU and ISP can
24 * can poll those with very low latency and cost. CPU access to indexes is
26 * interrupt triggered message handling. CPU doesn't need to poll indexes.
31 /* Shared structure between driver and FW - do not modify */
109 /* pass pkg_dir address to SPC in non-secure mode */
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/linux-6.12.1/drivers/spi/
Dspi-pxa2xx-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
21 #include "spi-pxa2xx.h"
28 struct spi_message *msg = drv_data->controller->cur_msg; in pxa2xx_spi_dma_transfer_complete()
31 * It is possible that one CPU is handling ROR interrupt and other in pxa2xx_spi_dma_transfer_complete()
36 if (atomic_dec_and_test(&drv_data->dma_running)) { in pxa2xx_spi_dma_transfer_complete()
38 * If the other CPU is still handling the ROR interrupt we in pxa2xx_spi_dma_transfer_complete()
39 * might not know about the error yet. So we re-check the in pxa2xx_spi_dma_transfer_complete()
43 error = read_SSSR_bits(drv_data, drv_data->mask_sr) & SSSR_ROR; in pxa2xx_spi_dma_transfer_complete()
46 clear_SSCR1_bits(drv_data, drv_data->dma_cr1); in pxa2xx_spi_dma_transfer_complete()
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