1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/irqchip/arm-gic.h>
25 #include "omap-secure.h"
26 #include "omap-wakeupgen.h"
52 static struct omap_smp_config cfg;  variable
71 	return cfg.scu_base;  in omap4_get_scu_base()
87 	 * BIT(27) - Disables streaming. All write-allocate lines allocate in  in omap5_erratum_workaround_801819()
89 	 * BIT(25) - Disables streaming. All write-allocate lines allocate in  in omap5_erratum_workaround_801819()
100 	pr_debug("%s: ARM erratum workaround 801819 applied on CPU%d\n",  in omap5_erratum_workaround_801819()
139 	pr_debug("%s: ARM ACR setup for CVE_2017_5715 applied on CPU%d\n",  in omap5_secondary_harden_predictor()
146 static void omap4_secondary_init(unsigned int cpu)  in omap4_secondary_init()  argument
150 	 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA  in omap4_secondary_init()
153 	 * OMAP443X GP devices- SMP bit isn't accessible.  in omap4_secondary_init()
154 	 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.  in omap4_secondary_init()
162 		 * Configure the CNTFRQ register for the secondary cpu's which  in omap4_secondary_init()
163 		 * indicates the frequency of the cpu local timers.  in omap4_secondary_init()
173 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)  in omap4_boot_secondary()  argument
182 	 * the AuxCoreBoot1 register is updated with cpu state  in omap4_boot_secondary()
190 			       cfg.wakeupgen_base + OMAP_AUX_CORE_BOOT_0);  in omap4_boot_secondary()
201 	 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to  in omap4_boot_secondary()
204 	 * More details can be found in OMAP4430 TRM - Version J  in omap4_boot_secondary()
214 		 * bit 1 == Non-Secure Enable  in omap4_boot_secondary()
215 		 * The Non-Secure banked register has not changed  in omap4_boot_secondary()
217 		 * GIC restoration will cause a problem to CPU0 Non-Secure SW.  in omap4_boot_secondary()
221 		 * 2) CPU1 must re-enable the GIC distributor on  in omap4_boot_secondary()
230 		 * Ensure that CPU power state is set to ON to avoid CPU  in omap4_boot_secondary()
250 	arch_send_wakeup_ipi_mask(cpumask_of(cpu));  in omap4_boot_secondary()
256  * Initialise the CPU possible map early - this describes the CPUs
270 		cfg.scu_base =  OMAP2_L4_IO_ADDRESS(scu_a9_get_base());  in omap4_smp_init_cpus()
271 		BUG_ON(!cfg.scu_base);  in omap4_smp_init_cpus()
272 		ncores = scu_get_core_count(cfg.scu_base);  in omap4_smp_init_cpus()
289  * For now, just make sure the start-up address is not within the booting
303  * up trying to use old kernel startup address or suspend-resume will
316 		released = readl_relaxed(cfg.wakeupgen_base +  in omap4_smp_maybe_reset_cpu1()
325 	cpu1_startup_pa = readl_relaxed(cfg.wakeupgen_base +  in omap4_smp_maybe_reset_cpu1()
344 	if (!needs_reset || !c->cpu1_rstctrl_va)  in omap4_smp_maybe_reset_cpu1()
350 	writel_relaxed(1, c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
351 	readl_relaxed(c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
352 	writel_relaxed(0, c->cpu1_rstctrl_va);  in omap4_smp_maybe_reset_cpu1()
371 	/* Must preserve cfg.scu_base set earlier */  in omap4_smp_prepare_cpus()
372 	cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa;  in omap4_smp_prepare_cpus()
373 	cfg.startup_addr = c->startup_addr;  in omap4_smp_prepare_cpus()
374 	cfg.wakeupgen_base = omap_get_wakeupgen_base();  in omap4_smp_prepare_cpus()
378 			cfg.startup_addr = omap5_secondary_hyp_startup;  in omap4_smp_prepare_cpus()
382 	cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4);  in omap4_smp_prepare_cpus()
383 	if (!cfg.cpu1_rstctrl_va)  in omap4_smp_prepare_cpus()
390 	if (cfg.scu_base)  in omap4_smp_prepare_cpus()
391 		scu_enable(cfg.scu_base);  in omap4_smp_prepare_cpus()
393 	omap4_smp_maybe_reset_cpu1(&cfg);  in omap4_smp_prepare_cpus()
402 		omap_auxcoreboot_addr(__pa_symbol(cfg.startup_addr));  in omap4_smp_prepare_cpus()
404 		writel_relaxed(__pa_symbol(cfg.startup_addr),  in omap4_smp_prepare_cpus()
405 			       cfg.wakeupgen_base + OMAP_AUX_CORE_BOOT_1);  in omap4_smp_prepare_cpus()