20 #include <linux/cpu.h>
40 #include <asm/cpu-features.h>
53 static void bmips_set_reset_vec(int cpu, u32 val);
59 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
63 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
64 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
72 #define CPUNUM(cpu, shift)		(((cpu) + bmips_cpu_offset) << (shift))  argument
73 #define ACTION_CLR_IPI(cpu, ipi)	(0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))  argument
74 #define ACTION_SET_IPI(cpu, ipi)	(0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))  argument
75 #define ACTION_BOOT_THREAD(cpu)		(0x08 | CPUNUM(cpu, 0))  argument
79 	int i, cpu = 1, boot_cpu = 0;  in bmips_smp_setup()  local
146 				__cpu_number_map[i] = cpu;  in bmips_smp_setup()
147 				__cpu_logical_map[cpu] = i;  in bmips_smp_setup()
148 				cpu++;  in bmips_smp_setup()
162  * IPI IRQ setup - runs on CPU0
189  * Tell the hardware to boot CPUx - runs on CPU0
191 static int bmips_boot_secondary(int cpu, struct task_struct *idle)  in bmips_boot_secondary()  argument
198 	 * Initial boot sequence for secondary CPU:  in bmips_boot_secondary()
199 	 *   bmips_reset_nmi_vec @ a000_0000 ->  in bmips_boot_secondary()
200 	 *   bmips_smp_entry ->  in bmips_boot_secondary()
201 	 *   plat_wired_tlb_setup (cached function call; optional) ->  in bmips_boot_secondary()
205 	 *   play_dead WAIT loop ->  in bmips_boot_secondary()
206 	 *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->  in bmips_boot_secondary()
207 	 *   eret to play_dead ->  in bmips_boot_secondary()
208 	 *   bmips_secondary_reentry ->  in bmips_boot_secondary()
212 	pr_info("SMP: Booting CPU%d...\n", cpu);  in bmips_boot_secondary()
214 	if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {  in bmips_boot_secondary()
215 		/* kseg1 might not exist if this CPU enabled XKS01 */  in bmips_boot_secondary()
216 		bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);  in bmips_boot_secondary()
221 			bmips43xx_send_ipi_single(cpu, 0);  in bmips_boot_secondary()
224 			bmips5000_send_ipi_single(cpu, 0);  in bmips_boot_secondary()
228 		bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);  in bmips_boot_secondary()
234 			if (cpu_logical_map(cpu) == 1)  in bmips_boot_secondary()
238 			write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));  in bmips_boot_secondary()
241 		cpumask_set_cpu(cpu, &bmips_booted_mask);  in bmips_boot_secondary()
248  * Early setup - runs on secondary CPU after cache probe
267  * Late setup - runs on secondary CPU before entering the idle loop
271 	pr_info("SMP: CPU%d is running\n", smp_processor_id());  in bmips_smp_finish()
284  * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
289 static void bmips5000_send_ipi_single(int cpu, unsigned int action)  in bmips5000_send_ipi_single()  argument
291 	write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));  in bmips5000_send_ipi_single()
296 	int action = irq - IPI0_IRQ;  in bmips5000_ipi_interrupt()
320  * We use one inbound SW IRQ for each CPU.
330 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)  in bmips43xx_send_ipi_single()  argument
335 	set_c0_cause(cpu ? C_SW1 : C_SW0);  in bmips43xx_send_ipi_single()
336 	per_cpu(ipi_action_mask, cpu) |= action;  in bmips43xx_send_ipi_single()
344 	int action, cpu = irq - IPI0_IRQ;  in bmips43xx_ipi_interrupt()  local
348 	per_cpu(ipi_action_mask, cpu) = 0;  in bmips43xx_ipi_interrupt()
349 	clear_c0_cause(cpu ? C_SW1 : C_SW0);  in bmips43xx_ipi_interrupt()
373 	unsigned int cpu = smp_processor_id();  in bmips_cpu_disable()  local
375 	pr_info("SMP: CPU%d is offline\n", cpu);  in bmips_cpu_disable()
377 	set_cpu_online(cpu, false);  in bmips_cpu_disable()
388 static void bmips_cpu_die(unsigned int cpu)  in bmips_cpu_die()  argument
469 	memcpy((void *)dst, start, end - start);  in bmips_wr_vec()
470 	dma_cache_wback(dst, end - start);  in bmips_wr_vec()
471 	local_flush_icache_range(dst, dst + (end - start));  in bmips_wr_vec()
484 	int cpu;  member
491 	int shift = info->cpu & 0x01 ? 16 : 0;  in bmips_set_reset_vec_remote()
492 	u32 mask = ~(0xffff << shift), val = info->val >> 16;  in bmips_set_reset_vec_remote()
499 		if (info->cpu & 0x02) {  in bmips_set_reset_vec_remote()
511 static void bmips_set_reset_vec(int cpu, u32 val)  in bmips_set_reset_vec()  argument
517 		info.cpu = cpu;  in bmips_set_reset_vec()
523 		if (cpu == 0)  in bmips_set_reset_vec()
550 		 *  - CPU1 will run this from uncached space  in bmips_ebase_setup()
551 		 *  - None of the cacheflush functions are set up yet  in bmips_ebase_setup()
553 		set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,  in bmips_ebase_setup()
586 	 * Called when starting/restarting a secondary CPU.  in plat_wired_tlb_setup()
596 	u32 __maybe_unused cfg;  in bmips_cpu_setup()  local
611 		cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
612 		__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
615 		cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
616 		__raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
619 		cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);  in bmips_cpu_setup()
620 		__raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);  in bmips_cpu_setup()
631 		cfg = __raw_readl(cbr + rac_addr);  in bmips_cpu_setup()
632 		__raw_writel(cfg | 0xf, cbr + rac_addr);  in bmips_cpu_setup()
636 		cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
637 		__raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);  in bmips_cpu_setup()
648 			cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);  in bmips_cpu_setup()
649 			__raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);  in bmips_cpu_setup()