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/linux-6.12.1/sound/core/seq/
Dseq_ump_convert.c1 // SPDX-License-Identifier: GPL-2.0-or-later
68 return port->ump_group ? (port->ump_group - 1) : 0; in get_ump_group()
76 * UMP -> MIDI1 sequencer event
85 ev->data.note.channel = val->note.channel; in ump_midi1_to_note_ev()
86 ev->data.note.note = val->note.note; in ump_midi1_to_note_ev()
87 ev->data.note.velocity = val->note.velocity; in ump_midi1_to_note_ev()
94 ev->data.control.channel = val->caf.channel; in ump_midi1_to_ctrl_ev()
95 ev->data.control.value = val->caf.data; in ump_midi1_to_ctrl_ev()
102 ev->data.control.channel = val->pb.channel; in ump_midi1_to_pitchbend_ev()
103 ev->data.control.value = (val->pb.data_msb << 7) | val->pb.data_lsb; in ump_midi1_to_pitchbend_ev()
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/linux-6.12.1/sound/soc/codecs/
Dssm2602.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
49 /*Left ADC Volume Control (SSM2602_REG_LEFT_ADC_VOL)*/
50 #define LINVOL_LIN_VOL 0x01F /* Left Channel PGA Volume control …
51 #define LINVOL_LIN_ENABLE_MUTE 0x080 /* Left Channel Input Mute …
52 #define LINVOL_LRIN_BOTH 0x100 /* Left Channel Line Input Volume update …
54 /*Right ADC Volume Control (SSM2602_REG_RIGHT_ADC_VOL)*/
55 #define RINVOL_RIN_VOL 0x01F /* Right Channel PGA Volume control …
56 #define RINVOL_RIN_ENABLE_MUTE 0x080 /* Right Channel Input Mute …
57 #define RINVOL_RLIN_BOTH 0x100 /* Right Channel Line Input Volume update …
59 /*Left DAC Volume Control (SSM2602_REG_LEFT_DAC_VOL)*/
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/linux-6.12.1/include/sound/
Dseq_midi_emul.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Midi channel definition for optional channel management.
15 * channel. All drivers for hardware that does not understand midi
20 int number; /* The channel number */
21 int client; /* The client associated with this channel */
22 int port; /* The port associated with this channel */
26 drum_channel:1, /* Drum channel */
31 unsigned char midi_pressure; /* Channel pressure */
35 unsigned char control[128]; /* Current value of all controls */ member
48 * The channel set consists of information describing the client and
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Dak4114.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #define AK4114_REG_FORMAT 0x01 /* format control */
13 #define AK4114_REG_IO0 0x02 /* input/output control */
14 #define AK4114_REG_IO1 0x03 /* input/output control */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
20 #define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */
21 #define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */
22 #define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */
23 #define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */
24 #define AK4114_REG_TXCSB0 0x0d /* TX channel status byte 0 */
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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Daudio-iio-aux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-iio-aux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Herve Codina <herve.codina@bootlin.com>
16 - $ref: dai-common.yaml#
20 const: audio-iio-aux
22 io-channels:
26 io-channel-names:
28 Industrial I/O channel names related to io-channels.
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/linux-6.12.1/sound/pci/
Dad1889.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
17 #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */
18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
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/linux-6.12.1/sound/pci/emu10k1/
Dp16v.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
11 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers …
15 …* The sample rate is also controlled by the same registers that control the rate of the EMU10K2 sa…
25 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
41 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
45 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
49 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
53 * [7:6] Capture input 3 channel select. 0 = Capture output 0.
57 * [9:8] Playback input 0 channel select. 0 = Play output 0.
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/linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/include/
Dbrcmu_d11.h1 // SPDX-License-Identifier: ISC
13 /* A chanspec (channel specification) holds the channel number, band,
14 * bandwidth and control sideband
20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
100 BRCMU_CHAN_SB_NONE = -1,
118 * struct brcmu_chan - stores channel formats
121 * channel info and the other way.
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/linux-6.12.1/drivers/dma/
Dep93xx_dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * arch/arm/mach-ep93xx/dma-m2p.c which has following copyrights:
14 * This driver is based on dw_dmac and amba-pl08x drivers.
20 #include <linux/dma-mapping.h>
139 * struct ep93xx_dma_desc - EP93xx specific transaction descriptor
146 * @node: link used for putting this into a channel queue
164 * struct ep93xx_dma_chan - an EP93xx DMA M2P/M2M channel
165 * @chan: dmaengine API channel
168 * @dma_cfg: channel number, direction
169 * @irq: interrupt number of the channel
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/linux-6.12.1/Documentation/sound/designs/
Dchannel-mapping-api.rst2 ALSA PCM channel-mapping API
10 The channel mapping API allows user to query the possible channel maps
11 and the current channel map, also optionally to modify the channel map
14 A channel map is an array of position for each PCM channel.
15 Typically, a stereo PCM stream has a channel map of
17 while a 4.0 surround PCM stream has a channel map of
20 The problem, so far, was that we had no standard channel map
21 explicitly, and applications had no way to know which channel
29 was no way to specify this because of lack of channel map
30 specification. These are the main motivations for the new channel
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/linux-6.12.1/drivers/hwmon/
Dpcf8591.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2001-2004 Aurelien Jarno <aurelien@aurel32.net>
31 * The PCF8591 control byte
52 * Channel selection
53 * 0x00 = channel 0
54 * 0x01 = channel 1
55 * 0x02 = channel 2
56 * 0x03 = channel 3
65 #define REG_TO_SIGNED(reg) (((reg) & 0x80) ? ((reg) - 256) : (reg))
71 u8 control; member
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/linux-6.12.1/drivers/tty/serial/
Dip22zilog.c1 // SPDX-License-Identifier: GPL-2.0
6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
51 #define ZS_WSYNC(channel) do { } while (0) argument
87 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
90 (UART_ZILOG(PORT)->curregs[REGNUM])
92 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
93 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
94 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
95 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
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Dsunzilog.c1 // SPDX-License-Identifier: GPL-2.0
48 /* On 32-bit sparcs we need to delay after register accesses
50 * On 64-bit sparc we only need to flush single writes to ensure
56 #define ZS_WSYNC(channel) do { } while (0) argument
61 readb(&((__channel)->control))
105 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
108 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
109 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
110 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
111 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
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Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 volatile unsigned char control; member
14 volatile unsigned char control;
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
142 /* Write Register 9 (Master interrupt control) */
149 #define CHRB 0x40 /* Reset channel B */
150 #define CHRA 0x80 /* Reset channel A */
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/linux-6.12.1/Documentation/networking/
Dppp_generic.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PPP Generic Driver and Channel Interface
12 The generic PPP driver in linux-2.4 provides an implementation of the
26 the services of PPP ``channels``. A PPP channel encapsulates a
28 PPP channel implementation can be arbitrarily complex internally but
31 handle ioctl requests. Currently there are PPP channel
36 natural and straightforward way, by allowing more than one channel to
42 PPP channel API
43 ---------------
49 Each channel has to provide two functions to the generic PPP layer,
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Dcdc_mbim.rst1 .. SPDX-License-Identifier: GPL-2.0
4 cdc_mbim - Driver for CDC MBIM Mobile Broadband modems
11 Network Control Model Devices" [2] optimized for Mobile Broadband
24 -----------
26 :Valid Range: N/Y (0-1)
44 provides a userspace interface to the MBIM control channel, and will
51 - mbimcli (included with the libmbim [3] library), and
52 - ModemManager [4]
57 - open the control channel
58 - configure network connection settings
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/linux-6.12.1/Documentation/sound/hd-audio/
Dcontrols.rst2 HD-Audio Codec-Specific Mixer Controls
6 This file explains the codec-specific mixer controls.
9 --------------
11 Channel Mode
12 This is an enum control to change the surround-channel setup,
16 jack-retasking of multi-I/O jacks.
18 Auto-Mute Mode
19 This is an enum control to change the auto-mute behavior of the
20 headphone and line-out jacks. If built-in speakers and headphone
21 and/or line-out jacks are available on a machine, this controls
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/linux-6.12.1/drivers/video/fbdev/
Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define LCCR0 (0x000) /* LCD Controller Control Register 0 */
9 #define LCCR1 (0x004) /* LCD Controller Control Register 1 */
10 #define LCCR2 (0x008) /* LCD Controller Control Register 2 */
11 #define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
12 #define LCCR4 (0x010) /* LCD Controller Control Register 4 */
13 #define LCCR5 (0x014) /* LCD Controller Control Register 5 */
18 #define TMEDCR (0x044) /* TMED Control Register */
20 #define FBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
21 #define FBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
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/linux-6.12.1/Documentation/virt/hyperv/
Dvmbus.rst1 .. SPDX-License-Identifier: GPL-2.0
5 VMBus is a software construct provided by Hyper-V to guest VMs. It
6 consists of a control path and common facilities used by synthetic
7 devices that Hyper-V presents to guest VMs. The control path is
11 and the synthetic device implementation that is part of Hyper-V, and
12 signaling primitives to allow Hyper-V and the guest to interrupt
17 establishes the VMBus control path with the Hyper-V host, then
21 Most synthetic devices offered by Hyper-V have a corresponding Linux
29 * PCI device pass-thru
34 * Key/Value Pair (KVP) exchange with Hyper-V
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/linux-6.12.1/Documentation/ABI/testing/
Dconfigfs-usb-gadget-uac21 What: /config/usb-gadget/gadget/functions/uac2.name
8 c_chmask capture channel mask
9 c_srate list of capture sampling rates (comma-separated)
11 c_hs_bint capture bInterval for HS/SS (1-4: fixed, 0: auto)
14 c_mute_present capture mute control enable
15 c_volume_present capture volume control enable
16 c_volume_min capture volume control min value
18 c_volume_max capture volume control max value
20 c_volume_res capture volume control resolution
23 p_chmask playback channel mask
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/linux-6.12.1/sound/mips/
Dsgio2audio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org>
15 #include <linux/dma-mapping.h>
25 #include <sound/control.h>
32 MODULE_AUTHOR("Vivien Chappelier <vivien.chappelier@linux-mips.org>");
36 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
52 #define CHANNEL_CONTROL_RESET BIT(10) /* 1: reset channel */
65 #define CHANNEL_RING_MASK (CHANNEL_RING_SIZE - 1)
78 /* definition of the chip-specific record */
87 struct snd_sgio2audio_chan channel[3]; member
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/linux-6.12.1/Documentation/hwmon/
Dltc2947.rst1 Kernel drivers ltc2947-i2c and ltc2947-spi
10 Addresses scanned: -
14 https://www.analog.com/media/en/technical-documentation/data-sheets/LTC2947.pdf
29 to control a fan as a function of measured temperature. Then, the GPIO becomes
31 temp2 channel is used to control this thresholds and to read the respective
37 The following attributes are supported. Limits are read-write, reset_history
38 is write-only and all the other attributes are read-only.
41 in0_input VP-VM voltage (mV).
49 in0_label Channel label (VP-VM)
59 in1_label Channel label (DVCC)
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/linux-6.12.1/Documentation/leds/
Dleds-lp5523.rst9 Contact: Samu Onkalo (samu.p.onkalo-at-nokia.com)
12 -----------
14 the led class control interface.
15 The name of each channel is configurable in the platform data - name and label.
16 There are three options to make the channel name.
20 To make specific channel name, then use 'name' platform data.
22 - /sys/class/leds/R1 (name: 'R1')
23 - /sys/class/leds/B1 (name: 'B1')
27 For one device name with channel number, then use 'label'.
28 - /sys/class/leds/RGB:channelN (label: 'RGB', N: 0 ~ 8)
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/linux-6.12.1/Documentation/devicetree/bindings/display/
Dmipi-dsi-bus.txt8 This document describes DSI bus-specific properties only or defines existing
25 - #address-cells: The number of cells required to represent an address on the
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
29 - #size-cells: Should be 0. There are cases where it makes sense to use a
33 - clock-master: boolean. Should be enabled if the host is being used in
42 Peripherals with DSI as control bus, or no control bus
43 ------------------------------------------------------
45 Peripherals with the DSI bus as the primary control bus, or peripherals with
46 no control bus but use the DSI bus to transmit pixel data are represented
49 device-specific properties.
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/linux-6.12.1/drivers/gpu/drm/bridge/analogix/
Danalogix-i2c-dptx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 /* HDCP Control Register 0 */
69 /* DP System Control Registers */
70 #define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1)
71 /* Bits for DP System Control Register 2 */
73 /* Bits for DP System Control Register 3 */
80 /* Bits for DP System Control Register 4 */
83 /* DP Video Control Register */
94 /* DP Audio Control Register */
102 /* Packet Send Control Register */
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