Lines Matching +full:control +full:- +full:channel
1 // SPDX-License-Identifier: GPL-2.0
6 * This is based on the drivers/serial/sunzilog.c code as of 2.6.0-test7 and the
13 * Copyright (C) 2002 Ralf Baechle (ralf@linux-mips.org)
51 #define ZS_WSYNC(channel) do { } while (0) argument
87 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel *)((PORT)->membase))
90 (UART_ZILOG(PORT)->curregs[REGNUM])
92 ((UART_ZILOG(PORT)->curregs[REGNUM]) = (REGVAL))
93 #define ZS_IS_CONS(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CONS)
94 #define ZS_IS_KGDB(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_KGDB)
95 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & IP22ZILOG_FLAG_MODEM_STATUS)
96 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & IP22ZILOG_FLAG_IS_CHANNEL_A)
97 #define ZS_REGS_HELD(UP) ((UP)->flags & IP22ZILOG_FLAG_REGS_HELD)
98 #define ZS_TX_STOPPED(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_STOPPED)
99 #define ZS_TX_ACTIVE(UP) ((UP)->flags & IP22ZILOG_FLAG_TX_ACTIVE)
104 * flip-flops which implement the settle time we do in software.
109 static unsigned char read_zsreg(struct zilog_channel *channel, in read_zsreg() argument
114 writeb(reg, &channel->control); in read_zsreg()
116 retval = readb(&channel->control); in read_zsreg()
122 static void write_zsreg(struct zilog_channel *channel, in write_zsreg() argument
125 writeb(reg, &channel->control); in write_zsreg()
127 writeb(value, &channel->control); in write_zsreg()
131 static void ip22zilog_clear_fifo(struct zilog_channel *channel) in ip22zilog_clear_fifo() argument
138 regval = readb(&channel->control); in ip22zilog_clear_fifo()
143 regval = read_zsreg(channel, R1); in ip22zilog_clear_fifo()
144 readb(&channel->data); in ip22zilog_clear_fifo()
148 writeb(ERR_RES, &channel->control); in ip22zilog_clear_fifo()
150 ZS_WSYNC(channel); in ip22zilog_clear_fifo()
158 static void __load_zsregs(struct zilog_channel *channel, unsigned char *regs) in __load_zsregs() argument
164 unsigned char stat = read_zsreg(channel, R1); in __load_zsregs()
170 writeb(ERR_RES, &channel->control); in __load_zsregs()
172 ZS_WSYNC(channel); in __load_zsregs()
174 ip22zilog_clear_fifo(channel); in __load_zsregs()
177 write_zsreg(channel, R1, in __load_zsregs()
181 write_zsreg(channel, R4, regs[R4]); in __load_zsregs()
183 /* Set misc. TX/RX control bits. */ in __load_zsregs()
184 write_zsreg(channel, R10, regs[R10]); in __load_zsregs()
187 write_zsreg(channel, R3, regs[R3] & ~RxENAB); in __load_zsregs()
188 write_zsreg(channel, R5, regs[R5] & ~TxENAB); in __load_zsregs()
191 write_zsreg(channel, R6, regs[R6]); in __load_zsregs()
192 write_zsreg(channel, R7, regs[R7]); in __load_zsregs()
195 * master interrupt control (R9). We make sure this is setup in __load_zsregs()
200 write_zsreg(channel, R14, regs[R14] & ~BRENAB); in __load_zsregs()
202 /* Clock mode control. */ in __load_zsregs()
203 write_zsreg(channel, R11, regs[R11]); in __load_zsregs()
206 write_zsreg(channel, R12, regs[R12]); in __load_zsregs()
207 write_zsreg(channel, R13, regs[R13]); in __load_zsregs()
210 write_zsreg(channel, R14, regs[R14]); in __load_zsregs()
212 /* External status interrupt control. */ in __load_zsregs()
213 write_zsreg(channel, R15, regs[R15]); in __load_zsregs()
216 write_zsreg(channel, R0, RES_EXT_INT); in __load_zsregs()
217 write_zsreg(channel, R0, RES_EXT_INT); in __load_zsregs()
220 write_zsreg(channel, R3, regs[R3]); in __load_zsregs()
221 write_zsreg(channel, R5, regs[R5]); in __load_zsregs()
224 write_zsreg(channel, R1, regs[R1]); in __load_zsregs()
227 /* Reprogram the Zilog channel HW registers with the copies found in the
234 struct zilog_channel *channel) in ip22zilog_maybe_update_regs() argument
238 up->flags |= IP22ZILOG_FLAG_REGS_HELD; in ip22zilog_maybe_update_regs()
240 __load_zsregs(channel, up->curregs); in ip22zilog_maybe_update_regs()
249 struct zilog_channel *channel) in ip22zilog_receive_chars() argument
253 bool push = up->port.state != NULL; in ip22zilog_receive_chars()
256 ch = readb(&channel->control); in ip22zilog_receive_chars()
261 r1 = read_zsreg(channel, R1); in ip22zilog_receive_chars()
263 writeb(ERR_RES, &channel->control); in ip22zilog_receive_chars()
265 ZS_WSYNC(channel); in ip22zilog_receive_chars()
268 ch = readb(&channel->data); in ip22zilog_receive_chars()
271 ch &= up->parity_mask; in ip22zilog_receive_chars()
275 r1 |= up->tty_break; in ip22zilog_receive_chars()
279 up->port.icount.rx++; in ip22zilog_receive_chars()
281 up->tty_break = 0; in ip22zilog_receive_chars()
284 up->port.icount.brk++; in ip22zilog_receive_chars()
290 up->port.icount.parity++; in ip22zilog_receive_chars()
292 up->port.icount.frame++; in ip22zilog_receive_chars()
294 up->port.icount.overrun++; in ip22zilog_receive_chars()
295 r1 &= up->port.read_status_mask; in ip22zilog_receive_chars()
304 if (uart_handle_sysrq_char(&up->port, ch)) in ip22zilog_receive_chars()
308 uart_insert_char(&up->port, r1, Rx_OVR, ch, flag); in ip22zilog_receive_chars()
314 struct zilog_channel *channel) in ip22zilog_status_handle() argument
318 status = readb(&channel->control); in ip22zilog_status_handle()
321 writeb(RES_EXT_INT, &channel->control); in ip22zilog_status_handle()
323 ZS_WSYNC(channel); in ip22zilog_status_handle()
325 if (up->curregs[R15] & BRKIE) { in ip22zilog_status_handle()
326 if ((status & BRK_ABRT) && !(up->prev_status & BRK_ABRT)) { in ip22zilog_status_handle()
327 if (uart_handle_break(&up->port)) in ip22zilog_status_handle()
328 up->tty_break = Rx_SYS; in ip22zilog_status_handle()
330 up->tty_break = Rx_BRK; in ip22zilog_status_handle()
336 up->port.icount.dsr++; in ip22zilog_status_handle()
342 if ((status ^ up->prev_status) ^ DCD) in ip22zilog_status_handle()
343 uart_handle_dcd_change(&up->port, in ip22zilog_status_handle()
345 if ((status ^ up->prev_status) ^ CTS) in ip22zilog_status_handle()
346 uart_handle_cts_change(&up->port, in ip22zilog_status_handle()
349 wake_up_interruptible(&up->port.state->port.delta_msr_wait); in ip22zilog_status_handle()
352 up->prev_status = status; in ip22zilog_status_handle()
356 struct zilog_channel *channel) in ip22zilog_transmit_chars() argument
362 unsigned char status = readb(&channel->control); in ip22zilog_transmit_chars()
371 * to poll on enough port->xmit space becoming free. -DaveM in ip22zilog_transmit_chars()
377 up->flags &= ~IP22ZILOG_FLAG_TX_ACTIVE; in ip22zilog_transmit_chars()
380 __load_zsregs(channel, up->curregs); in ip22zilog_transmit_chars()
381 up->flags &= ~IP22ZILOG_FLAG_REGS_HELD; in ip22zilog_transmit_chars()
385 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; in ip22zilog_transmit_chars()
389 if (up->port.x_char) { in ip22zilog_transmit_chars()
390 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; in ip22zilog_transmit_chars()
391 writeb(up->port.x_char, &channel->data); in ip22zilog_transmit_chars()
393 ZS_WSYNC(channel); in ip22zilog_transmit_chars()
395 up->port.icount.tx++; in ip22zilog_transmit_chars()
396 up->port.x_char = 0; in ip22zilog_transmit_chars()
400 if (up->port.state == NULL) in ip22zilog_transmit_chars()
402 tport = &up->port.state->port; in ip22zilog_transmit_chars()
403 if (uart_tx_stopped(&up->port)) in ip22zilog_transmit_chars()
405 if (!uart_fifo_get(&up->port, &c)) in ip22zilog_transmit_chars()
408 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; in ip22zilog_transmit_chars()
409 writeb(c, &channel->data); in ip22zilog_transmit_chars()
411 ZS_WSYNC(channel); in ip22zilog_transmit_chars()
413 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in ip22zilog_transmit_chars()
414 uart_write_wakeup(&up->port); in ip22zilog_transmit_chars()
419 writeb(RES_Tx_P, &channel->control); in ip22zilog_transmit_chars()
421 ZS_WSYNC(channel); in ip22zilog_transmit_chars()
429 struct zilog_channel *channel in ip22zilog_interrupt() local
430 = ZILOG_CHANNEL_FROM_PORT(&up->port); in ip22zilog_interrupt()
434 uart_port_lock(&up->port); in ip22zilog_interrupt()
435 r3 = read_zsreg(channel, R3); in ip22zilog_interrupt()
437 /* Channel A */ in ip22zilog_interrupt()
439 writeb(RES_H_IUS, &channel->control); in ip22zilog_interrupt()
441 ZS_WSYNC(channel); in ip22zilog_interrupt()
444 push = ip22zilog_receive_chars(up, channel); in ip22zilog_interrupt()
446 ip22zilog_status_handle(up, channel); in ip22zilog_interrupt()
448 ip22zilog_transmit_chars(up, channel); in ip22zilog_interrupt()
450 uart_port_unlock(&up->port); in ip22zilog_interrupt()
453 tty_flip_buffer_push(&up->port.state->port); in ip22zilog_interrupt()
455 /* Channel B */ in ip22zilog_interrupt()
456 up = up->next; in ip22zilog_interrupt()
457 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); in ip22zilog_interrupt()
460 uart_port_lock(&up->port); in ip22zilog_interrupt()
462 writeb(RES_H_IUS, &channel->control); in ip22zilog_interrupt()
464 ZS_WSYNC(channel); in ip22zilog_interrupt()
467 push = ip22zilog_receive_chars(up, channel); in ip22zilog_interrupt()
469 ip22zilog_status_handle(up, channel); in ip22zilog_interrupt()
471 ip22zilog_transmit_chars(up, channel); in ip22zilog_interrupt()
473 uart_port_unlock(&up->port); in ip22zilog_interrupt()
476 tty_flip_buffer_push(&up->port.state->port); in ip22zilog_interrupt()
478 up = up->next; in ip22zilog_interrupt()
489 struct zilog_channel *channel; in ip22zilog_read_channel_status() local
492 channel = ZILOG_CHANNEL_FROM_PORT(port); in ip22zilog_read_channel_status()
493 status = readb(&channel->control); in ip22zilog_read_channel_status()
544 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); in ip22zilog_set_mctrl() local
559 up->curregs[R5] |= set_bits; in ip22zilog_set_mctrl()
560 up->curregs[R5] &= ~clear_bits; in ip22zilog_set_mctrl()
561 write_zsreg(channel, R5, up->curregs[R5]); in ip22zilog_set_mctrl()
570 up->flags |= IP22ZILOG_FLAG_TX_STOPPED; in ip22zilog_stop_tx()
578 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); in ip22zilog_start_tx() local
581 up->flags |= IP22ZILOG_FLAG_TX_ACTIVE; in ip22zilog_start_tx()
582 up->flags &= ~IP22ZILOG_FLAG_TX_STOPPED; in ip22zilog_start_tx()
584 status = readb(&channel->control); in ip22zilog_start_tx()
591 /* Send the first character to jump-start the TX done in ip22zilog_start_tx()
594 if (port->x_char) { in ip22zilog_start_tx()
595 writeb(port->x_char, &channel->data); in ip22zilog_start_tx()
597 ZS_WSYNC(channel); in ip22zilog_start_tx()
599 port->icount.tx++; in ip22zilog_start_tx()
600 port->x_char = 0; in ip22zilog_start_tx()
602 struct tty_port *tport = &port->state->port; in ip22zilog_start_tx()
607 writeb(c, &channel->data); in ip22zilog_start_tx()
609 ZS_WSYNC(channel); in ip22zilog_start_tx()
611 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) in ip22zilog_start_tx()
612 uart_write_wakeup(&up->port); in ip22zilog_start_tx()
620 struct zilog_channel *channel; in ip22zilog_stop_rx() local
625 channel = ZILOG_CHANNEL_FROM_PORT(port); in ip22zilog_stop_rx()
628 up->curregs[R1] &= ~RxINT_MASK; in ip22zilog_stop_rx()
629 ip22zilog_maybe_update_regs(up, channel); in ip22zilog_stop_rx()
637 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); in ip22zilog_enable_ms() local
640 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE); in ip22zilog_enable_ms()
641 if (new_reg != up->curregs[R15]) { in ip22zilog_enable_ms()
642 up->curregs[R15] = new_reg; in ip22zilog_enable_ms()
645 write_zsreg(channel, R15, up->curregs[R15]); in ip22zilog_enable_ms()
654 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); in ip22zilog_break_ctl() local
667 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in ip22zilog_break_ctl()
668 if (new_reg != up->curregs[R5]) { in ip22zilog_break_ctl()
669 up->curregs[R5] = new_reg; in ip22zilog_break_ctl()
672 write_zsreg(channel, R5, up->curregs[R5]); in ip22zilog_break_ctl()
680 struct zilog_channel *channel; in __ip22zilog_reset() local
683 if (up->flags & IP22ZILOG_FLAG_RESET_DONE) in __ip22zilog_reset()
687 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); in __ip22zilog_reset()
689 unsigned char stat = read_zsreg(channel, R1); in __ip22zilog_reset()
697 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); in __ip22zilog_reset()
699 write_zsreg(channel, R9, FHWRES); in __ip22zilog_reset()
701 (void) read_zsreg(channel, R0); in __ip22zilog_reset()
703 up->flags |= IP22ZILOG_FLAG_RESET_DONE; in __ip22zilog_reset()
704 up->next->flags |= IP22ZILOG_FLAG_RESET_DONE; in __ip22zilog_reset()
709 struct zilog_channel *channel; in __ip22zilog_startup() local
711 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); in __ip22zilog_startup()
715 __load_zsregs(channel, up->curregs); in __ip22zilog_startup()
717 write_zsreg(channel, R9, up->curregs[R9]); in __ip22zilog_startup()
718 up->prev_status = readb(&channel->control); in __ip22zilog_startup()
721 up->curregs[R3] |= RxENAB; in __ip22zilog_startup()
722 up->curregs[R5] |= TxENAB; in __ip22zilog_startup()
724 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in __ip22zilog_startup()
725 ip22zilog_maybe_update_regs(up, channel); in __ip22zilog_startup()
743 * The test for ZS_IS_CONS is explained by the following e-mail:
748 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
764 * do the normal software shutdown - ie, free irqs etc)
770 struct zilog_channel *channel; in ip22zilog_shutdown() local
778 channel = ZILOG_CHANNEL_FROM_PORT(port); in ip22zilog_shutdown()
781 up->curregs[R3] &= ~RxENAB; in ip22zilog_shutdown()
782 up->curregs[R5] &= ~TxENAB; in ip22zilog_shutdown()
785 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); in ip22zilog_shutdown()
786 up->curregs[R5] &= ~SND_BRK; in ip22zilog_shutdown()
787 ip22zilog_maybe_update_regs(up, channel); in ip22zilog_shutdown()
800 up->curregs[R10] = NRZ; in ip22zilog_convert_to_zs()
801 up->curregs[R11] = TCBR | RCBR; in ip22zilog_convert_to_zs()
804 up->curregs[R4] &= ~XCLK_MASK; in ip22zilog_convert_to_zs()
805 up->curregs[R4] |= X16CLK; in ip22zilog_convert_to_zs()
806 up->curregs[R12] = brg & 0xff; in ip22zilog_convert_to_zs()
807 up->curregs[R13] = (brg >> 8) & 0xff; in ip22zilog_convert_to_zs()
808 up->curregs[R14] = BRENAB; in ip22zilog_convert_to_zs()
811 up->curregs[3] &= ~RxN_MASK; in ip22zilog_convert_to_zs()
812 up->curregs[5] &= ~TxN_MASK; in ip22zilog_convert_to_zs()
815 up->curregs[3] |= Rx5; in ip22zilog_convert_to_zs()
816 up->curregs[5] |= Tx5; in ip22zilog_convert_to_zs()
817 up->parity_mask = 0x1f; in ip22zilog_convert_to_zs()
820 up->curregs[3] |= Rx6; in ip22zilog_convert_to_zs()
821 up->curregs[5] |= Tx6; in ip22zilog_convert_to_zs()
822 up->parity_mask = 0x3f; in ip22zilog_convert_to_zs()
825 up->curregs[3] |= Rx7; in ip22zilog_convert_to_zs()
826 up->curregs[5] |= Tx7; in ip22zilog_convert_to_zs()
827 up->parity_mask = 0x7f; in ip22zilog_convert_to_zs()
831 up->curregs[3] |= Rx8; in ip22zilog_convert_to_zs()
832 up->curregs[5] |= Tx8; in ip22zilog_convert_to_zs()
833 up->parity_mask = 0xff; in ip22zilog_convert_to_zs()
836 up->curregs[4] &= ~0x0c; in ip22zilog_convert_to_zs()
838 up->curregs[4] |= SB2; in ip22zilog_convert_to_zs()
840 up->curregs[4] |= SB1; in ip22zilog_convert_to_zs()
842 up->curregs[4] |= PAR_ENAB; in ip22zilog_convert_to_zs()
844 up->curregs[4] &= ~PAR_ENAB; in ip22zilog_convert_to_zs()
846 up->curregs[4] |= PAR_EVEN; in ip22zilog_convert_to_zs()
848 up->curregs[4] &= ~PAR_EVEN; in ip22zilog_convert_to_zs()
850 up->port.read_status_mask = Rx_OVR; in ip22zilog_convert_to_zs()
852 up->port.read_status_mask |= CRC_ERR | PAR_ERR; in ip22zilog_convert_to_zs()
854 up->port.read_status_mask |= BRK_ABRT; in ip22zilog_convert_to_zs()
856 up->port.ignore_status_mask = 0; in ip22zilog_convert_to_zs()
858 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR; in ip22zilog_convert_to_zs()
860 up->port.ignore_status_mask |= BRK_ABRT; in ip22zilog_convert_to_zs()
862 up->port.ignore_status_mask |= Rx_OVR; in ip22zilog_convert_to_zs()
866 up->port.ignore_status_mask = 0xff; in ip22zilog_convert_to_zs()
881 uart_port_lock_irqsave(&up->port, &flags); in ip22zilog_set_termios()
885 ip22zilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg); in ip22zilog_set_termios()
887 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) in ip22zilog_set_termios()
888 up->flags |= IP22ZILOG_FLAG_MODEM_STATUS; in ip22zilog_set_termios()
890 up->flags &= ~IP22ZILOG_FLAG_MODEM_STATUS; in ip22zilog_set_termios()
893 uart_update_timeout(port, termios->c_cflag, baud); in ip22zilog_set_termios()
895 uart_port_unlock_irqrestore(&up->port, flags); in ip22zilog_set_termios()
900 return "IP22-Zilog"; in ip22zilog_type()
923 return -EINVAL; in ip22zilog_verify_port()
949 static int zilog_irq = -1;
964 panic("IP22-Zilog: Cannot allocate IP22-Zilog tables."); in ip22zilog_alloc_tables()
968 /* Get the address of the registers for IP22-Zilog instance CHIP. */
974 panic("IP22-Zilog: Illegal chip number %d in get_zs.", chip); in get_zs()
977 /* Not probe-able, hard code it. */ in get_zs()
978 base = (unsigned long) &sgioc->uart; in get_zs()
981 request_mem_region(base, 8, "IP22-Zilog"); in get_zs()
991 struct zilog_channel *channel = ZILOG_CHANNEL_FROM_PORT(port); in ip22zilog_put_char() local
995 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM in ip22zilog_put_char()
998 unsigned char val = readb(&channel->control); in ip22zilog_put_char()
1004 } while (--loops); in ip22zilog_put_char()
1006 writeb(ch, &channel->data); in ip22zilog_put_char()
1008 ZS_WSYNC(channel); in ip22zilog_put_char()
1014 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; in ip22zilog_console_write()
1017 uart_port_lock_irqsave(&up->port, &flags); in ip22zilog_console_write()
1018 uart_console_write(&up->port, s, count, ip22zilog_put_char); in ip22zilog_console_write()
1020 uart_port_unlock_irqrestore(&up->port, flags); in ip22zilog_console_write()
1025 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; in ip22zilog_console_setup()
1031 up->flags |= IP22ZILOG_FLAG_IS_CONS; in ip22zilog_console_setup()
1033 printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index); in ip22zilog_console_setup()
1035 uart_port_lock_irqsave(&up->port, &flags); in ip22zilog_console_setup()
1037 up->curregs[R15] |= BRKIE; in ip22zilog_console_setup()
1041 uart_port_unlock_irqrestore(&up->port, flags); in ip22zilog_console_setup()
1045 return uart_set_options(&up->port, con, baud, parity, bits, flow); in ip22zilog_console_setup()
1056 .index = -1,
1078 int channel, chip; in ip22zilog_prepare() local
1083 for (channel = 0; channel < NUM_CHANNELS; channel++) in ip22zilog_prepare()
1084 spin_lock_init(&ip22zilog_port_table[channel].port.lock); in ip22zilog_prepare()
1086 ip22zilog_irq_chain = &ip22zilog_port_table[NUM_CHANNELS - 1]; in ip22zilog_prepare()
1088 for (channel = NUM_CHANNELS - 1 ; channel > 0; channel--) in ip22zilog_prepare()
1089 up[channel].next = &up[channel - 1]; in ip22zilog_prepare()
1090 up[channel].next = NULL; in ip22zilog_prepare()
1096 up[(chip * 2) + 0].port.membase = (char *) &rp->channelB; in ip22zilog_prepare()
1097 up[(chip * 2) + 1].port.membase = (char *) &rp->channelA; in ip22zilog_prepare()
1101 (unsigned long) ioremap((unsigned long) &rp->channelB, 8); in ip22zilog_prepare()
1103 (unsigned long) ioremap((unsigned long) &rp->channelA, 8); in ip22zilog_prepare()
1106 /* Channel A */ in ip22zilog_prepare()
1118 /* Channel B */ in ip22zilog_prepare()
1130 for (channel = 0; channel < NUM_CHANNELS; channel++) { in ip22zilog_prepare()
1131 struct uart_ip22zilog_port *up = &ip22zilog_port_table[channel]; in ip22zilog_prepare()
1135 up->parity_mask = 0xff; in ip22zilog_prepare()
1136 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB; in ip22zilog_prepare()
1137 up->curregs[R4] = PAR_EVEN | X16CLK | SB1; in ip22zilog_prepare()
1138 up->curregs[R3] = RxENAB | Rx8; in ip22zilog_prepare()
1139 up->curregs[R5] = TxENAB | Tx8; in ip22zilog_prepare()
1140 up->curregs[R9] = NV | MIE; in ip22zilog_prepare()
1141 up->curregs[R10] = NRZ; in ip22zilog_prepare()
1142 up->curregs[R11] = TCBR | RCBR; in ip22zilog_prepare()
1144 up->curregs[R12] = (brg & 0xff); in ip22zilog_prepare()
1145 up->curregs[R13] = (brg >> 8) & 0xff; in ip22zilog_prepare()
1146 up->curregs[R14] = BRENAB; in ip22zilog_prepare()
1159 "IP22-Zilog", ip22zilog_irq_chain)) { in ip22zilog_ports_init()
1160 panic("IP22-Zilog: Unable to register zs interrupt handler.\n"); in ip22zilog_ports_init()
1170 uart_add_one_port(&ip22zilog_reg, &up->port); in ip22zilog_ports_init()
1194 uart_remove_one_port(&ip22zilog_reg, &up->port); in ip22zilog_exit()
1217 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");