Lines Matching +full:control +full:- +full:channel

1 /* SPDX-License-Identifier: GPL-2.0-only */
20 /* HDCP Control Register 0 */
69 /* DP System Control Registers */
70 #define SP_DP_SYSTEM_CTRL_BASE		(0x80 - 1)
71 /* Bits for DP System Control Register 2 */
73 /* Bits for DP System Control Register 3 */
80 /* Bits for DP System Control Register 4 */
83 /* DP Video Control Register */
94 /* DP Audio Control Register */
102 /* Packet Send Control Register */
113 /* DP HDCP Control Register */
130 /* DP Lane 0 Link Training Control Register */
138 /* DP Link Training Control Register */
151 /* DP CEP Training Control Registers */
160 /* DP Polling Control Register */
164 /* DP Link Debug Control Register */
171 /* AUX Misc control Register */
174 /* DP PLL control Register */
182 /* DP Misc Control Register */
192 /* DP Downspread Control Register 1 */
195 /* DP M Value Calculation Control Register */
199 /* AUX Channel Access Status Register */
203 /* AUX Channel DEFER Control Register */
212 /* DP AUX Channel Control Register 1 */
228 /* DP AUX Channel Control Register 2 */
236 /* DP Video Stream Control InfoFrame Register */
243 /* DP AUX Channel Control Register 3 */
247 /* DP AUX Channel Control Register 4 */