Lines Matching +full:control +full:- +full:channel
1 /* SPDX-License-Identifier: GPL-2.0 */
10 volatile unsigned char control; member
14 volatile unsigned char control;
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
142 /* Write Register 9 (Master interrupt control) */
149 #define CHRB 0x40 /* Reset channel B */
150 #define CHRA 0x80 /* Reset channel A */
153 /* Write Register 10 (misc control bits) */
165 /* Write Register 11 (Clock Mode control) */
185 /* Write Register 14 (Misc control bits) */
199 /* Write Register 15 (external/status interrupt control) */
235 /* Read Register 2 (channel b only) - Interrupt vector */
247 #define CHBEXT 0x1 /* Channel B Ext/Stat IP */
248 #define CHBTxIP 0x2 /* Channel B Tx IP */
249 #define CHBRxIP 0x4 /* Channel B Rx IP */
250 #define CHAEXT 0x8 /* Channel A Ext/Stat IP */
251 #define CHATxIP 0x10 /* Channel A Tx IP */
252 #define CHARxIP 0x20 /* Channel A Rx IP */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \ argument
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \ argument
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \ argument
277 readb(&channel->data); \
279 readb(&channel->data); \