sound/pci/ad1889.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org>
9 #define AD_DS_WSMC	0x00 /* wave/synthesis channel mixer control */
10 #define  AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
12 #define  AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */
13 #define  AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */
14 #define  AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */
17 #define AD_DS_RAMC	0x02 /* resampler/ADC channel mixer control */
18 #define  AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */
19 #define  AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */
20 #define  AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */
22 #define  AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */
25 #define AD_DS_WADA	0x04 /* wave channel mix attenuation */
31 #define AD_DS_SYDA	0x06 /* synthesis channel mix attenuation */
37 #define AD_DS_WAS	0x08 /* wave channel sample rate */
40 #define AD_DS_RES	0x0a /* resampler channel sample rate */
43 #define AD_DS_CCS	0x0c /* chip control/status */
44 #define  AD_DS_CCS_ADO   0x0001 /* ADC channel overflow */
45 #define  AD_DS_CCS_REO   0x0002 /* resampler channel overflow */
46 #define  AD_DS_CCS_SYU   0x0004 /* synthesis channel underflow */
47 #define  AD_DS_CCS_WAU   0x0008 /* wave channel underflow */
48 /* bits 4 -> 7, 9, 11 -> 14 reserved */
49 #define  AD_DS_CCS_XTD   0x0100 /* xtd delay control (4096 clock cycles) */
87 /* bits 24 -> 31 reserved */
90 #define AD_DMA_ADC	0xa8	/* ADC      dma control and status */
91 #define AD_DMA_SYNTH	0xb0	/* Synth    dma control and status */
92 #define AD_DMA_WAV	0xb8	/* wave     dma control and status */
93 #define AD_DMA_RES	0xa0	/* Resample dma control and status */
105 /* bits 8 -> 15 reserved */
108 #define  AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */
109 #define  AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */
110 #define  AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */
111 #define  AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */
114 /* bits 7 -> 13 reserved */
119 /* bits 19 -> 31 reserved */
126 #define AD_DMA_CHSS	0xc4 /* dma channel stop status */
127 #define  AD_DMA_CHSS_RESS 0x000001 /* resampler channel stopped */
128 #define  AD_DMA_CHSS_ADCS 0x000002 /* ADC channel stopped */
129 #define  AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */
130 #define  AD_DMA_CHSS_WAVS 0x000008 /* wave channel stopped */
132 #define AD_GPIO_IPC	0xc8	/* gpio port control */
146 #define AD_MISC_CTL     0x176 /* misc control */
157 #define AD_AC97_ACIC	0x180 /* ac97 codec interface control */
165 /* bits 10 -> 14 reserved */