| /linux-6.12.1/drivers/clk/sophgo/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
2 # common clock support for SOPHGO SoC family.
5 tristate "Support for the Sophgo CV1800 series SoCs clock controller"
8 This driver supports clock controller of Sophgo CV18XX series SoC.
9 The driver require a 25MHz Oscillator to function generate clock.
10 It includes PLLs, common clock function and some vendor clock for
14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
18 Sophgo SG2042 SoC. This clock IP uses three oscillators with
23 tristate "Sophgo SG2042 Clock Generator support"
[all …]
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| /linux-6.12.1/drivers/tty/serial/ |
| D | ip22zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
118 #define X32CLK 0x80 /* x32 clock mode */
119 #define X64CLK 0xC0 /* x64 clock mode */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
165 /* Write Register 11 (Clock Mode control) */
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| D | zs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
38 * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
135 #define X1CLK 0x0 /* x1 clock mode */
136 #define X16CLK 0x40 /* x16 clock mode */
137 #define X32CLK 0x80 /* x32 clock mode */
138 #define X64CLK 0xc0 /* x64 clock mode */
144 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
[all …]
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| D | sunzilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
108 #define X1CLK 0x0 /* x1 clock mode */
109 #define X16CLK 0x40 /* x16 clock mode */
110 #define X32CLK 0x80 /* x32 clock mode */
111 #define X64CLK 0xC0 /* x64 clock mode */
118 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
128 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
130 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
167 /* Write Register 11 (Clock Mode control) */
[all …]
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| D | pmac_zilog.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
[all …]
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| /linux-6.12.1/drivers/net/hamradio/ |
| D | z8530.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
82 #define X1CLK 0x0 /* x1 clock mode */
83 #define X16CLK 0x40 /* x16 clock mode */
84 #define X32CLK 0x80 /* x32 clock mode */
85 #define X64CLK 0xC0 /* x64 clock mode */
91 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
129 /* Write Register 11 (Clock Mode control) */
131 #define TRxCTC 1 /* TRxC = Transmit clock */
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| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | renesas,5p35023.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 The 5P35023 is a VersaClock programmable clock generator and
14 is designed for low-power, consumer, and high-performance PCI
25 boots. Any configuration not supported by the common clock framework
29 …sas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-pr…
[all …]
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| D | silabs,si514.txt | 1 Binding for Silicon Labs 514 programmable I2C clock generator.
4 This binding uses the common clock binding[1]. Details about the device can be
7 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible: Shall be "silabs,si514"
13 - reg: I2C device address.
14 - #clock-cells: From common clock bindings: Shall be 0.
17 - clock-output-names: From common clock bindings. Recommended to be "si514".
20 si514: clock-generator@55 {
22 #clock-cells = <0>;
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| D | armada3700-tbg-clock.txt | 1 * Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
3 Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
6 The TBG clock consumer should specify the desired clock by having the
7 clock ID in its "clocks" phandle cell.
9 The following is a list of provided IDs and clock names on Armada 3700:
16 - compatible : shall be "marvell,armada-3700-tbg-clock"
17 - reg : must be the register address of North Bridge PLL register
18 - #clock-cells : from common clock binding; shall be set to 1
23 compatible = "marvell,armada-3700-tbg-clock";
26 #clock-cells = <1>;
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| D | adi,axi-clkgen.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Michael Hennerich <michael.hennerich@analog.com>
14 The axi_clkgen IP core is a software programmable clock generator,
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
[all …]
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| D | renesas,cpg-mstp-clocks.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
18 and the clock index in the group, from 0 to 31.
23 - enum:
24 - renesas,r7s72100-mstp-clocks # RZ/A1
[all …]
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| D | renesas,rzv2h-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
14 and control of clock signals for the IP modules, generation and control of resets,
19 const: renesas,r9a09g057-cpg
26 - description: AUDIO_EXTAL clock input
[all …]
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| D | renesas,rzg2l-cpg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
15 similar, but does not have Clock Monitor Registers.
18 - The CPG block generates various core clocks,
19 - The Module Standby Mode block provides two functions:
[all …]
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| /linux-6.12.1/drivers/clk/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
6 The <linux/clk.h> calls support software clock gating and
16 Select this option when the clock API in <linux/clk.h> is implemented
22 bool "Common Clock Framework"
28 The common clock framework is a single definition of struct
30 implementation of the clock API in include/linux/clk.h.
37 tristate "Clock driver for WM831x/2x PMICs"
54 tristate "Ti LMK04832 JESD204B Compliant Clock Jitter Cleaner"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
62 tristate "Clock driver for Apple SoC NCOs"
[all …]
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| /linux-6.12.1/include/soc/fsl/qe/ |
| D | qe.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
35 QE_BRG1, /* Baud Rate Generator 1 */
36 QE_BRG2, /* Baud Rate Generator 2 */
37 QE_BRG3, /* Baud Rate Generator 3 */
38 QE_BRG4, /* Baud Rate Generator 4 */
39 QE_BRG5, /* Baud Rate Generator 5 */
40 QE_BRG6, /* Baud Rate Generator 6 */
41 QE_BRG7, /* Baud Rate Generator 7 */
42 QE_BRG8, /* Baud Rate Generator 8 */
43 QE_BRG9, /* Baud Rate Generator 9 */
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,v-tc.txt | 2 ------------------------------------
4 The Video Timing Controller is a general purpose video timing generator and
9 - compatible: Must be "xlnx,v-tc-6.1".
11 - reg: Physical base address and length of the registers set for the device.
13 - clocks: Must contain a clock specifier for the VTC core and timing
14 interfaces clock.
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
21 At least one of the xlnx,detector and xlnx,generator properties must be
28 compatible = "xlnx,v-tc-6.1";
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| /linux-6.12.1/Documentation/gpu/amdgpu/display/ |
| D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
34 * PCLK: Pixel Clock
35 * SYMCLK: Symbol Clock
36 * SOCCLK: GPU Engine Clock
37 * DISPCLK: Display Clock
38 * DPPCLK: DPP Clock
39 * DCFCLK: Display Controller Fabric Clock
40 * REFCLK: Real Time Reference Clock
42 * FCLK: Fabric Clock
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| /linux-6.12.1/Documentation/ABI/testing/ |
| D | sysfs-timecard | 18 uses for clock adjustments.
24 IRIG adjustments from external IRIG-B signal
35 10Mhz signal is used as the 10Mhz reference clock
42 IRIG signal is sent to the IRIG-B module
57 10Mhz output is from the 10Mhz reference clock
58 PHC output PPS is from the PHC clock
59 MAC output PPS is from the Miniature Atomic Clock
62 IRIG output is from the PHC, in IRIG-B format
64 GEN1 output is from frequency generator 1
65 GEN2 output is from frequency generator 2
[all …]
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| /linux-6.12.1/drivers/iio/frequency/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
5 # Clock Distribution device drivers
6 # Phase-Locked Loop (PLL) frequency synthesizers
12 menu "Clock Generator/Distribution"
15 tristate "Analog Devices AD9523 Low Jitter Clock Generator"
19 Clock Generator. The driver provides direct access via sysfs.
27 # Phase-Locked Loop (PLL) frequency synthesizers
30 menu "Phase-Locked Loop (PLL) frequency synthesizers"
100 Downconverter with integrated Fractional-N PLL and VCO.
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| /linux-6.12.1/Documentation/devicetree/bindings/ptp/ |
| D | fsl,ptp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/rng/ |
| D | microchip,pic32-rng.txt | 1 * Microchip PIC32 Random Number Generator
3 The PIC32 RNG provides a pseudo random number generator which can be seeded by
4 another true random number generator.
7 - compatible : should be "microchip,pic32mzda-rng"
8 - reg : Specifies base physical address and size of the registers.
9 - clocks: clock phandle.
14 compatible = "microchip,pic32mzda-rng";
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| /linux-6.12.1/drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 struct mipi_dsi_device *dsi = adv->dsi; in adv7511_dsi_config_timing_gen()
30 struct drm_display_mode *mode = &adv->curr_mode; in adv7511_dsi_config_timing_gen()
34 hsw = mode->hsync_end - mode->hsync_start; in adv7511_dsi_config_timing_gen()
35 hfp = mode->hsync_start - mode->hdisplay; in adv7511_dsi_config_timing_gen()
36 hbp = mode->htotal - mode->hsync_end; in adv7511_dsi_config_timing_gen()
37 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
38 vfp = mode->vsync_start - mode->vdisplay; in adv7511_dsi_config_timing_gen()
39 vbp = mode->vtotal - mode->vsync_end; in adv7511_dsi_config_timing_gen()
41 /* set pixel clock divider mode */ in adv7511_dsi_config_timing_gen()
[all …]
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| /linux-6.12.1/drivers/clk/qcom/ |
| D | clk-rcg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/clk-provider.h>
8 #include "clk-regmap.h"
10 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
20 #define C(s, h, m, n) { (s), (2 * (h) - 1), (m), (n) }
38 * struct mn - M/N:D counter
60 * struct pre_div - pre-divider
70 * struct src_sel - source selector
81 * struct clk_rcg - root clock generator
89 * @clkr: regmap clock handle
[all …]
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| /linux-6.12.1/arch/m68k/atari/ |
| D | atasound.c | 7 * unknown. (++roman: That's me... :-)
13 * 1998-05-31 ++andreas: atari_mksound rewritten to always use the envelope,
42 /* Busy wait for data being completely sent :-( */ in atari_microwire_cmd()
56 /* Generates sound of some frequency for some number of clock in atari_mksound()
65 /* Disable generator A in mixer control. */ in atari_mksound()
79 /* Set generator A frequency to hz. */ in atari_mksound()
93 /* Envelope form: max -> min single. */ in atari_mksound()
96 /* Use envelope for generator A. */ in atari_mksound()
100 /* Set generator A level to maximum, no envelope. */ in atari_mksound()
104 /* Turn on generator A in mixer control. */ in atari_mksound()
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| /linux-6.12.1/include/linux/platform_data/ |
| D | ad7793.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
11 * enum ad7793_clock_source - AD7793 clock source selection
12 * @AD7793_CLK_SRC_INT: Internal 64 kHz clock, not available at the CLK pin.
13 * @AD7793_CLK_SRC_INT_CO: Internal 64 kHz clock, available at the CLK pin.
14 * @AD7793_CLK_SRC_EXT: Use external clock.
15 * @AD7793_CLK_SRC_EXT_DIV2: Use external clock divided by 2.
25 * enum ad7793_bias_voltage - AD7793 bias voltage selection
26 * @AD7793_BIAS_VOLTAGE_DISABLED: Bias voltage generator disabled
27 * @AD7793_BIAS_VOLTAGE_AIN1: Bias voltage connected to AIN1(-).
28 * @AD7793_BIAS_VOLTAGE_AIN2: Bias voltage connected to AIN2(-).
[all …]
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