fsl/qe/qe.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
35 	QE_BRG1,		/* Baud Rate Generator 1 */
36 	QE_BRG2,		/* Baud Rate Generator 2 */
37 	QE_BRG3,		/* Baud Rate Generator 3 */
38 	QE_BRG4,		/* Baud Rate Generator 4 */
39 	QE_BRG5,		/* Baud Rate Generator 5 */
40 	QE_BRG6,		/* Baud Rate Generator 6 */
41 	QE_BRG7,		/* Baud Rate Generator 7 */
42 	QE_BRG8,		/* Baud Rate Generator 8 */
43 	QE_BRG9,		/* Baud Rate Generator 9 */
44 	QE_BRG10,		/* Baud Rate Generator 10 */
45 	QE_BRG11,		/* Baud Rate Generator 11 */
46 	QE_BRG12,		/* Baud Rate Generator 12 */
47 	QE_BRG13,		/* Baud Rate Generator 13 */
48 	QE_BRG14,		/* Baud Rate Generator 14 */
49 	QE_BRG15,		/* Baud Rate Generator 15 */
50 	QE_BRG16,		/* Baud Rate Generator 16 */
51 	QE_CLK1,		/* Clock 1 */
52 	QE_CLK2,		/* Clock 2 */
53 	QE_CLK3,		/* Clock 3 */
54 	QE_CLK4,		/* Clock 4 */
55 	QE_CLK5,		/* Clock 5 */
56 	QE_CLK6,		/* Clock 6 */
57 	QE_CLK7,		/* Clock 7 */
58 	QE_CLK8,		/* Clock 8 */
59 	QE_CLK9,		/* Clock 9 */
60 	QE_CLK10,		/* Clock 10 */
61 	QE_CLK11,		/* Clock 11 */
62 	QE_CLK12,		/* Clock 12 */
63 	QE_CLK13,		/* Clock 13 */
64 	QE_CLK14,		/* Clock 14 */
65 	QE_CLK15,		/* Clock 15 */
66 	QE_CLK16,		/* Clock 16 */
67 	QE_CLK17,		/* Clock 17 */
68 	QE_CLK18,		/* Clock 18 */
69 	QE_CLK19,		/* Clock 19 */
70 	QE_CLK20,		/* Clock 20 */
71 	QE_CLK21,		/* Clock 21 */
72 	QE_CLK22,		/* Clock 22 */
73 	QE_CLK23,		/* Clock 23 */
74 	QE_CLK24,		/* Clock 24 */
112 	return -ENOSYS;  in cpm_muram_alloc()
118 	return -ENOSYS;  in devm_cpm_muram_alloc()
128 	return -ENOSYS;  in cpm_muram_alloc_fixed()
135 	return -ENOSYS;  in devm_cpm_muram_alloc_fixed()
145 	return -ENOSYS;  in cpm_muram_offset()
184 static inline int par_io_init(struct device_node *np) { return -ENOSYS; }  in par_io_init()
185 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }  in par_io_of_config()
187 		int assignment, int has_irq) { return -ENOSYS; }  in par_io_config_pin()
188 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }  in par_io_data_set()
203 	return ERR_PTR(-ENOSYS);  in qe_pin_request()
216 	return -ENOSYS;  in qe_issue_cmd()
290 	u8 id[62];      /* Null-terminated identifier string */
291 	u8 split;	/* 0 = shared I-RAM, 1 = split I-RAM */
303 		u8 id[32];      	/* Null-terminated identifier */
306 		__be32 iram_offset;     /* Offset into I-RAM for the code */
307 		__be32 count;   	/* Number of 32-bit words of the code */
331 	return -ENOSYS;  in qe_upload_firmware()
495 /* QE CECR Sub Block - sub block of QE command.
529 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
578 #define QE_CP_CERCR_MEE		0x8000	/* Multi-user RAM ECC enable */
582 /* I-RAM */