Lines Matching +full:clock +full:- +full:generator
1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
116 #define X1CLK 0x0 /* x1 clock mode */
117 #define X16CLK 0x40 /* x16 clock mode */
118 #define X32CLK 0x80 /* x32 clock mode */
119 #define X64CLK 0xC0 /* x64 clock mode */
126 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
136 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
138 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
165 /* Write Register 11 (Clock Mode control) */
167 #define TRxCTC 1 /* TRxC = Transmit clock */
168 #define TRxCBR 2 /* TRxC = BR Generator Output */
171 #define TCRTxCP 0 /* Transmit clock = RTxC pin */
172 #define TCTRxCP 8 /* Transmit clock = TRxC pin */
173 #define TCBR 0x10 /* Transmit clock = BR Generator output */
174 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
175 #define RCRTxCP 0 /* Receive clock = RTxC pin */
176 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
177 #define RCBR 0x40 /* Receive clock = BR Generator output */
178 #define RCDPLL 0x60 /* Receive clock = DPLL output */
181 /* Write Register 12 (lower byte of baud rate generator time constant) */
183 /* Write Register 13 (upper byte of baud rate generator time constant) */
186 #define BRENAB 1 /* Baud rate generator enable */
187 #define BRSRC 2 /* Baud rate generator source */
192 #define RMC 0x40 /* Reset missing clock */
194 #define SSBR 0x80 /* Set DPLL source = BR generator */
235 /* Read Register 2 (channel b only) - Interrupt vector */
260 #define CLK1MIS 0x80 /* One clock missing */
262 /* Read Register 12 (lower byte of baud rate generator constant) */
264 /* Read Register 13 (upper byte of baud rate generator constant) */
269 #define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \
272 #define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \
275 #define ZS_CLEARFIFO(channel) do { readb(&channel->data); \
277 readb(&channel->data); \
279 readb(&channel->data); \