tty/serial/pmac_zilog.h

1 /* SPDX-License-Identifier: GPL-2.0 */
25 	 * of "escc" node (ie. ch-a or ch-b)
64 	if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)  in pmz_get_port_A()
66 	return uap->mate;  in pmz_get_port_A()
78 		writeb(reg, port->control_reg);  in read_zsreg()
79 	return readb(port->control_reg);  in read_zsreg()
85 		writeb(reg, port->control_reg);  in write_zsreg()
86 	writeb(value, port->control_reg);  in write_zsreg()
91 	return readb(port->data_reg);  in read_zsdata()
96 	writeb(data, port->data_reg);  in write_zsdata()
101 	(void)readb(port->control_reg);  in zssync()
108 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
110 #define ZS_CLOCK         3686400	/* Z8530 RTxC input clock rate */
196 #define	X1CLK		0x0	/* x1 clock mode */
197 #define	X16CLK		0x40	/* x16 clock mode */
198 #define	X32CLK		0x80	/* x32 clock mode */
199 #define	X64CLK		0xC0	/* x64 clock mode */
206 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
216 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
218 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
248 /* Write Register 11 (Clock Mode control) */
250 #define	TRxCTC	1	/* TRxC = Transmit clock */
251 #define	TRxCBR	2	/* TRxC = BR Generator Output */
254 #define	TCRTxCP	0	/* Transmit clock = RTxC pin */
255 #define	TCTRxCP	8	/* Transmit clock = TRxC pin */
256 #define	TCBR	0x10	/* Transmit clock = BR Generator output */
257 #define	TCDPLL	0x18	/* Transmit clock = DPLL output */
258 #define	RCRTxCP	0	/* Receive clock = RTxC pin */
259 #define	RCTRxCP	0x20	/* Receive clock = TRxC pin */
260 #define	RCBR	0x40	/* Receive clock = BR Generator output */
261 #define	RCDPLL	0x60	/* Receive clock = DPLL output */
264 /* Write Register 12 (lower byte of baud rate generator time constant) */
266 /* Write Register 13 (upper byte of baud rate generator time constant) */
269 #define	BRENAB	1	/* Baud rate generator enable */
270 #define	BRSRC	2	/* Baud rate generator source */
275 #define	RMC	0x40	/* Reset missing clock */
277 #define	SSBR	0x80	/* Set DPLL source = BR generator */
283 #define	EN85C30	1	/* Enable some 85c30-enhanced registers */
320 /* Read Register 2 (channel b only) - Interrupt vector */
345 #define	CLK1MIS	0x80		/* One clock missing */
347 /* Read Register 12 (lower byte of baud rate generator constant) */
349 /* Read Register 13 (upper byte of baud rate generator constant) */
361 #define ZS_IS_CONS(UP)			((UP)->flags & PMACZILOG_FLAG_IS_CONS)
362 #define ZS_IS_KGDB(UP)			((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
363 #define ZS_IS_CHANNEL_A(UP)		((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
364 #define ZS_REGS_HELD(UP)		((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
365 #define ZS_TX_STOPPED(UP)		((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
366 #define ZS_TX_ACTIVE(UP)		((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
367 #define ZS_WANTS_MODEM_STATUS(UP)	((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
368 #define ZS_IS_IRDA(UP)			((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
369 #define ZS_IS_INTMODEM(UP)		((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
370 #define ZS_IS_OPEN(UP)			((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
371 #define ZS_IS_EXTCLK(UP)		((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)