tty/serial/zs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
38  * Per-SCC state for locking and the interrupt handler.
53 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
135 #define X1CLK		0x0	/* x1 clock mode */
136 #define X16CLK		0x40	/* x16 clock mode */
137 #define X32CLK		0x80	/* x32 clock mode */
138 #define X64CLK		0xc0	/* x64 clock mode */
144 #define SDLC_CRC	0x4	/* SDLC/CRC-16 */
154 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
156 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
184 /* Write Register 11 (Clock Mode Control) */
186 #define TRxCTC		1	/* TRxC = Transmit clock */
187 #define TRxCBR		2	/* TRxC = BR Generator Output */
190 #define TCRTxCP		0	/* Transmit clock = RTxC pin */
191 #define TCTRxCP		8	/* Transmit clock = TRxC pin */
192 #define TCBR		0x10	/* Transmit clock = BR Generator output */
193 #define TCDPLL		0x18	/* Transmit clock = DPLL output */
194 #define RCRTxCP		0	/* Receive clock = RTxC pin */
195 #define RCTRxCP		0x20	/* Receive clock = TRxC pin */
196 #define RCBR		0x40	/* Receive clock = BR Generator output */
197 #define RCDPLL		0x60	/* Receive clock = DPLL output */
200 /* Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) */
202 /* Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) */
205 #define BRENABL		1	/* Baud rate generator enable */
206 #define BRSRC		2	/* Baud rate generator source */
211 #define RMC		0x40	/* Reset missing clock */
213 #define SSBR		0x80	/* Set DPLL source = BR generator */
255 /* Read Register 2 (Interrupt Vector (WR2) -- channel A).  */
257 /* Read Register 2 (Modified Interrupt Vector -- channel B).  */
259 /* Read Register 3 (Interrupt Pending Bits -- channel A only).  */
277 #define CLK1MIS		0x80	/* One clock missing */
279 /* Read Register 12 (Lower Byte of Baud Rate Generator Constant (WR12)) */
281 /* Read Register 13 (Upper Byte of Baud Rate Generator Constant (WR13) */