Lines Matching +full:clock +full:- +full:generator

1 /* SPDX-License-Identifier: GPL-2.0 */
82 #define	X1CLK		0x0	/* x1 clock mode */
83 #define	X16CLK		0x40	/* x16 clock mode */
84 #define	X32CLK		0x80	/* x32 clock mode */
85 #define	X64CLK		0xC0	/* x64 clock mode */
91 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
100 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
102 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
129 /* Write Register 11 (Clock Mode control) */
131 #define	TRxCTC	1	/* TRxC = Transmit clock */
132 #define	TRxCBR	2	/* TRxC = BR Generator Output */
135 #define	TCRTxCP	0	/* Transmit clock = RTxC pin */
136 #define	TCTRxCP	8	/* Transmit clock = TRxC pin */
137 #define	TCBR	0x10	/* Transmit clock = BR Generator output */
138 #define	TCDPLL	0x18	/* Transmit clock = DPLL output */
139 #define	RCRTxCP	0	/* Receive clock = RTxC pin */
140 #define	RCTRxCP	0x20	/* Receive clock = TRxC pin */
141 #define	RCBR	0x40	/* Receive clock = BR Generator output */
142 #define	RCDPLL	0x60	/* Receive clock = DPLL output */
145 /* Write Register 12 (lower byte of baud rate generator time constant) */
147 /* Write Register 13 (upper byte of baud rate generator time constant) */
150 #define	BRENABL	1	/* Baud rate generator enable */
151 #define	BRSRC	2	/* Baud rate generator source */
156 #define	RMC	0x40	/* Reset missing clock */
158 #define	SSBR	0x80	/* Set DPLL source = BR generator */
199 /* Read Register 2 (channel b only) - Interrupt vector */
215 #define	CLK1MIS	0x80		/* One clock missing */
217 /* Read Register 12 (lower byte of baud rate generator constant) */
219 /* Read Register 13 (upper byte of baud rate generator constant) */