| /linux-6.12.1/drivers/net/ethernet/qlogic/qed/ |
| D | qed_hsi.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
147 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3
158 __le16 reserved[3];
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3
206 __le16 reserved[3];
240 __le32 reserved1[3];
256 u8 reserved[3];
329 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
359 #define CORE_TX_BD_TX_DST_MASK 0x3
[all …]
|
| /linux-6.12.1/arch/x86/crypto/ |
| D | serpent-sse2-x86_64-asm_64.S | 41 #define S0_1(x0, x1, x2, x3, x4) \ argument
42 movdqa x3, x4; \
43 por x0, x3; \
47 pxor x1, x3; \
51 #define S0_2(x0, x1, x2, x3, x4) \ argument
52 pxor x3, x0; \
56 pxor x2, x3; \
61 #define S1_1(x0, x1, x2, x3, x4) \ argument
64 pxor x3, x0; \
65 pxor RNOT, x3; \
[all …]
|
| D | serpent-sse2-i586-asm_32.S | 42 #define K(x0, x1, x2, x3, x4, i) \ argument
49 get_key(i, 3, x4); \
50 pxor x4, x3;
52 #define LK(x0, x1, x2, x3, x4, i) \ argument
59 pslld $3, x2; \
60 psrld $(32 - 3), x4; \
68 pslld $3, x4; \
69 pxor x2, x3; \
70 pxor x4, x3; \
71 movdqa x3, x4; \
[all …]
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| D | serpent-avx-x86_64-asm_64.S | 20 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
51 #define S0_1(x0, x1, x2, x3, x4) \ argument
52 vpor x0, x3, tp; \
53 vpxor x3, x0, x0; \
54 vpxor x2, x3, x4; \
56 vpxor x1, tp, x3; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
61 vpxor x3, x0, x0; \
65 vpxor x2, x3, x3; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
[all …]
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| D | serpent-avx2-asm_64.S | 21 .byte 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0
51 #define S0_1(x0, x1, x2, x3, x4) \ argument
52 vpor x0, x3, tp; \
53 vpxor x3, x0, x0; \
54 vpxor x2, x3, x4; \
56 vpxor x1, tp, x3; \
60 #define S0_2(x0, x1, x2, x3, x4) \ argument
61 vpxor x3, x0, x0; \
65 vpxor x2, x3, x3; \
70 #define S1_1(x0, x1, x2, x3, x4) \ argument
[all …]
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| /linux-6.12.1/crypto/ |
| D | serpent_generic.c | 27 #define loadkeys(x0, x1, x2, x3, i) \ argument
28 ({ x0 = k[i]; x1 = k[i+1]; x2 = k[i+2]; x3 = k[i+3]; })
30 #define storekeys(x0, x1, x2, x3, i) \ argument
31 ({ k[i] = x0; k[i+1] = x1; k[i+2] = x2; k[i+3] = x3; })
33 #define store_and_load_keys(x0, x1, x2, x3, s, l) \ argument
34 ({ storekeys(x0, x1, x2, x3, s); loadkeys(x0, x1, x2, x3, l); })
36 #define K(x0, x1, x2, x3, i) ({ \ argument
37 x3 ^= k[4*(i)+3]; x2 ^= k[4*(i)+2]; \
41 #define LK(x0, x1, x2, x3, x4, i) ({ \ argument
43 x2 = rol32(x2, 3); x1 ^= x0; x4 = x0 << 3; \
[all …]
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| /linux-6.12.1/sound/soc/codecs/ |
| D | rt5677.h | 354 #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
363 #define RT5677_SLB_ADC4_MASK (0x3 << 6)
365 #define RT5677_SLB_ADC3_MASK (0x3 << 4)
367 #define RT5677_SLB_ADC2_MASK (0x3 << 2)
369 #define RT5677_SLB_ADC1_MASK (0x3 << 0)
388 /* Analog DAC1/2/3 Source Control (0x15) */
389 #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
391 #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
407 #define RT5677_M_DAC3_R_VOL (0x1 << 3)
408 #define RT5677_M_DAC3_R_VOL_SFT 3
[all …]
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| D | rt1318.h | 105 #define RT1318_PLLIN_MCLK (0x3 << 4)
114 #define RT1318_SYSCLK_PLL2B (0x3 << 0)
120 #define RT1318_DIV_AP_MASK (0x3 << 4)
125 #define RT1318_DIV_AP_DIV8 (0x3 << 4)
126 #define RT1318_DIV_DAMOD_MASK (0x3 << 0)
131 #define RT1318_DIV_DAMOD_DIV8 (0x3 << 0)
132 /* Clock-3 (0xC004) */
138 #define RT1318_AD_STO1_DIV8 (0x3 << 4)
145 #define RT1318_AD_STO2_DIV8 (0x3 << 0)
154 #define RT1318_AD_ANA_STO1_DIV8 (0x3 << 4)
[all …]
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| D | mt6359.h | 267 #define RG_AUDACCDETVIN1PULLLOW_SFT 3
269 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
436 #define RG_EINT0CEN_SFT 3
438 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
515 #define ACCDET_DSN_CBS_MASK 0x3
516 #define ACCDET_DSN_CBS_MASK_SFT (0x3 << 0)
520 #define ACCDET_DSN_BIX_MASK 0x3
521 #define ACCDET_DSN_BIX_MASK_SFT (0x3 << 2)
570 #define RG_AUDACCDETRSV_MASK 0x3
571 #define RG_AUDACCDETRSV_MASK_SFT (0x3 << 13)
[all …]
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| D | tscs454.h | 18 #define R_IRQMASK VIRT_ADDR(0x0, 0x3)
70 #define R_HSDSTAT VIRT_ADDR(0x1, 0x3)
102 #define R_SUBCTL VIRT_ADDR(0x2, 0x3)
126 #define R_SPKEQFILT VIRT_ADDR(0x3, 0x1)
127 #define R_SPKCRWDL VIRT_ADDR(0x3, 0x2)
128 #define R_SPKCRWDM VIRT_ADDR(0x3, 0x3)
129 #define R_SPKCRWDH VIRT_ADDR(0x3, 0x4)
130 #define R_SPKCRRDL VIRT_ADDR(0x3, 0x5)
131 #define R_SPKCRRDM VIRT_ADDR(0x3, 0x6)
132 #define R_SPKCRRDH VIRT_ADDR(0x3, 0x7)
[all …]
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| D | rt5631.h | 216 #define RT5631_MIC1_BOOST_CTRL_30DB (0x3 << 12)
228 #define RT5631_MIC2_BOOST_CTRL_30DB (0x3 << 8)
244 #define RT5631_MICBIAS1_SHORT_CURR_DET_MASK (0x3 << 4)
249 #define RT5631_MICBIAS2_VOLT_CTRL_MASK (0x1 << 3)
250 #define RT5631_MICBIAS2_VOLT_CTRL_90P (0x0 << 3)
251 #define RT5631_MICBIAS2_VOLT_CTRL_75P (0x1 << 3)
257 #define RT5631_MICBIAS2_SHORT_CURR_DET_MASK (0x3)
280 #define RT5631_DMIC_CLK_CTRL_MASK (0x3 << 4)
322 #define RT5631_SPK_L_MUX_SEL_MASK (0x3 << 14)
325 #define RT5631_SPK_L_MUX_SEL_DAC_L (0x3 << 14)
[all …]
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| D | rt5616.h | 218 #define RT5616_ADC_L_BST_MASK (0x3 << 14)
220 #define RT5616_ADC_R_BST_MASK (0x3 << 12)
222 #define RT5616_ADC_COMP_MASK (0x3 << 10)
278 #define RT5616_STO_DD_R2_VOL_MASK (0x1 << 3)
279 #define RT5616_STO_DD_R2_VOL_SFT 3
314 #define RT5616_DAC_L2_SEL_MASK (0x3 << 14)
319 #define RT5616_DAC_L2_SEL_BASS (0x3 << 14)
320 #define RT5616_DAC_R2_SEL_MASK (0x3 << 12)
333 #define RT5616_RXDC_SEL_MASK (0x3 << 8)
338 #define RT5616_RXDC_SEL_SWAP (0x3 << 8)
[all …]
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| D | rt5651.h | 261 #define RT5651_ADC_L_BST_MASK (0x3 << 14)
263 #define RT5651_ADC_R_BST_MASK (0x3 << 12)
265 #define RT5651_ADC_COMP_MASK (0x3 << 10)
307 #define RT5651_STO2_ADC_R2_SRC_MASK (0x1 << 3)
308 #define RT5651_STO2_ADC_R2_SRC_SFT 3
309 #define RT5651_STO2_ADC_R2_SRC_DMIC (0x0 << 3)
310 #define RT5651_STO2_ADC_R2_SRC_DACMIXR (0x1 << 3)
341 #define RT5651_DAC_R2_STO_R_VOL_MASK (0x1 << 3)
342 #define RT5651_DAC_R2_STO_R_VOL_SFT 3
367 #define RT5651_STO_DD_R2_VOL_MASK (0x1 << 3)
[all …]
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| /linux-6.12.1/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 86 {PXA168_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
95 {PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
97 {PXA168_CLK_PLL1_2_3_16, "pll1_2_3_16", "pll1_2", 3, 16, 0},
163 …arent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI0, 4, 3, 0, &twsi0_lock},
164 …arent_names, ARRAY_SIZE(twsi_parent_names), CLK_SET_RATE_PARENT, APBC_TWSI1, 4, 3, 0, &twsi1_lock},
165 …{0, "kpc_mux", kpc_parent_names, ARRAY_SIZE(kpc_parent_names), CLK_SET_RATE_PARENT, APBC_KPC, 4, 3…
166 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM0, 4, 3, 0, &pwm0_lock},
167 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM1, 4, 3, 0, &pwm1_lock},
168 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM2, 4, 3, 0, &pwm2_lock},
169 …m_parent_names, ARRAY_SIZE(pwm_parent_names), CLK_SET_RATE_PARENT, APBC_PWM3, 4, 3, 0, &pwm3_lock},
[all …]
|
| D | clk-of-pxa910.c | 69 {PXA910_CLK_PLL1_6, "pll1_6", "pll1_2", 1, 3, 0},
76 {PXA910_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
77 {PXA910_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
78 {PXA910_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
128 …arent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART0, 4, 3, 0, &uart0_lock},
129 …arent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_UART1, 4, 3, 0, &uart1_lock},
130 …p_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP0, 4, 3, 0, &ssp0_lock},
131 …p_parent_names, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, APBC_SSP1, 4, 3, 0, &ssp1_lock},
132 …nt_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER0, 4, 3, 0, &timer0_lock},
133 …nt_names, ARRAY_SIZE(timer_parent_names), CLK_SET_RATE_PARENT, APBC_TIMER1, 4, 3, 0, &timer1_lock},
[all …]
|
| D | clk-of-pxa1928.c | 51 {0, "pll1_416", "pll1_624", 2, 3, 0},
99 …, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART0 * 4, 4, 3, 0, &uart0_lock},
100 …, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART1 * 4, 4, 3, 0, &uart1_lock},
101 …, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART2 * 4, 4, 3, 0, &uart2_lock},
102 …, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_UART3 * 4, 4, 3, 0, &uart3_lock},
103 …mes, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP0 * 4, 4, 3, 0, &ssp0_lock},
104 …mes, ARRAY_SIZE(ssp_parent_names), CLK_SET_RATE_PARENT, PXA1928_CLK_SSP1 * 4, 4, 3, 0, &ssp1_lock},
108 …{PXA1928_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0…
109 …{PXA1928_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0…
110 …{PXA1928_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0…
[all …]
|
| /linux-6.12.1/drivers/pinctrl/sunxi/ |
| D | pinctrl-sun20i-d1.c | 22 SUNXI_FUNCTION(0x3, "ir"), /* TX */
33 SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT3 */
44 SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT2 */
51 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
55 SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT1 */
61 SUNXI_FUNCTION_IRQ_BANK(0xe, 0, 3)),
66 SUNXI_FUNCTION(0x3, "i2s2_dout"), /* DOUT0 */
77 SUNXI_FUNCTION(0x3, "i2s2"), /* BCLK */
88 SUNXI_FUNCTION(0x3, "i2s2"), /* LRCK */
99 SUNXI_FUNCTION(0x3, "i2s2"), /* MCLK */
[all …]
|
| D | pinctrl-sun6i-a31.c | 25 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
33 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
41 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
45 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
49 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
52 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
57 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
65 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
73 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
81 SUNXI_FUNCTION_VARIANT(0x3, "lcd1",
[all …]
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| D | pinctrl-sun50i-a100.c | 21 SUNXI_FUNCTION(0x3, "spi2"), /* CS */
28 SUNXI_FUNCTION(0x3, "spi2"), /* CLK */
35 SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */
38 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
42 SUNXI_FUNCTION(0x3, "spi2"), /* MISO */
44 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
49 SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */
56 SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */
62 SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */
69 SUNXI_FUNCTION(0x3, "i2s0_dout0"), /* DOUT0 */
[all …]
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| D | pinctrl-sun9i-a80.c | 39 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
44 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
134 SUNXI_FUNCTION(0x3, "uart3"), /* TX */
139 SUNXI_FUNCTION(0x3, "uart3"), /* RX */
146 SUNXI_FUNCTION(0x3, "mcsi"), /* MCLK */
151 SUNXI_FUNCTION(0x3, "mcsi"), /* SCK */
157 SUNXI_FUNCTION(0x3, "mcsi"), /* SDA */
166 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
171 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
176 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
[all …]
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| /linux-6.12.1/drivers/gpu/drm/i915/gt/ |
| D | intel_gpu_commands.h | 25 #define INSTR_RC_CLIENT 0x3
55 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
79 #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
109 #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
110 #define MI_SEMAPHORE_SYNC_MASK (3<<16)
114 #define MI_SAVE_EXT_STATE_EN (1<<3)
118 #define HSW_MI_RS_SAVE_STATE_EN (1<<3)
123 #define MI_SEMAPHORE_WAIT_TOKEN MI_INSTR(0x1c, 3) /* GEN12+ */
129 #define MI_SEMAPHORE_SAD_LTE_SDD (3 << 12)
137 #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
[all …]
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| /linux-6.12.1/drivers/usb/dwc2/ |
| D | hw.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
33 #define GOTGCTL_VBVALOVAL BIT(3)
57 #define GAHBCFG_HBSTLEN_INCR4 3
91 #define GUSBCFG_PHYIF16 BIT(3)
92 #define GUSBCFG_PHYIF8 (0 << 3)
107 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_50 0x3
119 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
155 #define GINTSTS_SOF BIT(3)
169 #define GRXSTS_PKTSTS_OUTDONE 3
170 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
[all …]
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| /linux-6.12.1/drivers/net/ethernet/broadcom/ |
| D | cnic_defs.h | 33 #define L5CM_RAMROD_CMD_ID_TCP_CONNECT (L5CM_RAMROD_CMD_ID_BASE + 3)
96 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
97 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
110 #define L4_KCQ_RAMROD_COMPLETION (0x1<<3) /* Everest only */
111 #define L4_KCQ_RAMROD_COMPLETION_SHIFT 3
208 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
209 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
218 #define L4_KWQ_CONNECT_REQ1_RSRV (0x1F<<3)
219 #define L4_KWQ_CONNECT_REQ1_RSRV_SHIFT 3
242 u8 rsrv1[3];
[all …]
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| /linux-6.12.1/drivers/scsi/bnx2i/ |
| D | 57xx_iscsi_hsi.h | 61 u32 reserved7[3];
118 u32 reserved2[3];
124 #define ISCSI_CLEANUP_REQUEST_TYPE (0x3<<14)
130 #define ISCSI_CLEANUP_REQUEST_TYPE (0x3<<14)
160 u32 reserved1[3];
177 #define ISCSI_CLEANUP_RESPONSE_TYPE (0x3<<14)
183 #define ISCSI_CLEANUP_RESPONSE_TYPE (0x3<<14)
200 #define ISCSI_CMD_REQUEST_RESERVED1 (0x3<<3)
201 #define ISCSI_CMD_REQUEST_RESERVED1_SHIFT 3
214 #define ISCSI_CMD_REQUEST_RESERVED1 (0x3<<3)
[all …]
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| /linux-6.12.1/include/linux/qed/ |
| D | fcoe_common.h | 1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
19 #define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
24 #define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
59 __le32 opaque[3];
80 #define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
169 #define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
171 #define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
173 #define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
187 #define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
229 #define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
[all …]
|