Lines Matching +full:3 +full:x3
354 #define RT5677_MICBIAS1_OVTH_MASK (0x3 << 9)
363 #define RT5677_SLB_ADC4_MASK (0x3 << 6)
365 #define RT5677_SLB_ADC3_MASK (0x3 << 4)
367 #define RT5677_SLB_ADC2_MASK (0x3 << 2)
369 #define RT5677_SLB_ADC1_MASK (0x3 << 0)
388 /* Analog DAC1/2/3 Source Control (0x15) */
389 #define RT5677_ANA_DAC3_SRC_SEL_MASK (0x3 << 4)
391 #define RT5677_ANA_DAC1_2_SRC_SEL_MASK (0x3 << 0)
407 #define RT5677_M_DAC3_R_VOL (0x1 << 3)
408 #define RT5677_M_DAC3_R_VOL_SFT 3
441 #define RT5677_M_DAC2_R_VOL (0x1 << 3)
442 #define RT5677_M_DAC2_R_VOL_SFT 3
459 #define RT5677_STO1_ADC_L_BST_MASK (0x3 << 14)
461 #define RT5677_STO1_ADC_R_BST_MASK (0x3 << 12)
463 #define RT5677_STO1_ADC_COMP_MASK (0x3 << 10)
465 #define RT5677_STO2_ADC_L_BST_MASK (0x3 << 8)
467 #define RT5677_STO2_ADC_R_BST_MASK (0x3 << 6)
469 #define RT5677_STO2_ADC_COMP_MASK (0x3 << 4)
479 #define RT5677_MONO_ADC_L_BST_MASK (0x3 << 14)
481 #define RT5677_MONO_ADC_R_BST_MASK (0x3 << 12)
483 #define RT5677_MONO_ADC_COMP_MASK (0x3 << 10)
486 /* Stereo 3/4 ADC Boost Gain Control (0x21) */
487 #define RT5677_STO3_ADC_L_BST_MASK (0x3 << 14)
489 #define RT5677_STO3_ADC_R_BST_MASK (0x3 << 12)
491 #define RT5677_STO3_ADC_COMP_MASK (0x3 << 10)
493 #define RT5677_STO4_ADC_L_BST_MASK (0x3 << 8)
495 #define RT5677_STO4_ADC_R_BST_MASK (0x3 << 6)
497 #define RT5677_STO4_ADC_COMP_MASK (0x3 << 4)
517 #define RT5677_SEL_STO4_ADC1_MASK (0x3 << 12)
519 #define RT5677_SEL_STO4_ADC2_MASK (0x3 << 10)
521 #define RT5677_SEL_STO4_DMIC_MASK (0x3 << 8)
533 #define RT5677_SEL_STO3_ADC1_MASK (0x3 << 12)
535 #define RT5677_SEL_STO3_ADC2_MASK (0x3 << 10)
537 #define RT5677_SEL_STO3_DMIC_MASK (0x3 << 8)
549 #define RT5677_SEL_STO2_ADC1_MASK (0x3 << 12)
551 #define RT5677_SEL_STO2_ADC2_MASK (0x3 << 10)
553 #define RT5677_SEL_STO2_DMIC_MASK (0x3 << 8)
569 #define RT5677_SEL_STO1_ADC1_MASK (0x3 << 12)
571 #define RT5677_SEL_STO1_ADC2_MASK (0x3 << 10)
573 #define RT5677_SEL_STO1_DMIC_MASK (0x3 << 8)
585 #define RT5677_SEL_MONO_ADC_L1_MASK (0x3 << 12)
587 #define RT5677_SEL_MONO_ADC_L2_MASK (0x3 << 10)
589 #define RT5677_SEL_MONO_DMIC_L_MASK (0x3 << 8)
595 #define RT5677_SEL_MONO_ADC_R1_MASK (0x3 << 4)
597 #define RT5677_SEL_MONO_ADC_R2_MASK (0x3 << 2)
599 #define RT5677_SEL_MONO_DMIC_R_MASK (0x3 << 0)
613 #define RT5677_ADDA1_SEL_MASK (0x3 << 0)
637 #define RT5677_M_DAC2_R_STO_R (0x1 << 3)
638 #define RT5677_M_DAC2_R_STO_R_SFT 3
667 #define RT5677_M_DAC1_R_MONO_R (0x1 << 3)
668 #define RT5677_M_DAC1_R_MONO_R_SFT 3
701 #define RT5677_M_DAC3_R_DD1_R (0x1 << 3)
702 #define RT5677_M_DAC3_R_DD1_R_SFT 3
735 #define RT5677_M_DAC4_R_DD2_R (0x1 << 3)
736 #define RT5677_M_DAC4_R_DD2_R_SFT 3
745 #define RT5677_IF3_DAC_SEL_MASK (0x3 << 6)
747 #define RT5677_IF3_ADC_SEL_MASK (0x3 << 4)
755 #define RT5677_IF4_DAC_SEL_MASK (0x3 << 2)
757 #define RT5677_IF4_ADC_SEL_MASK (0x3 << 0)
763 #define RT5677_SEL_PDM1_L_MASK (0x3 << 12)
767 #define RT5677_SEL_PDM1_R_MASK (0x3 << 8)
771 #define RT5677_SEL_PDM2_L_MASK (0x3 << 4)
773 #define RT5677_M_PDM2_R (0x1 << 3)
774 #define RT5677_M_PDM2_R_SFT 3
775 #define RT5677_SEL_PDM2_R_MASK (0x3 << 0)
783 #define RT5677_PDM_PATTERN (0x1 << 3)
785 #define RT5677_PDM_DIV_MASK (0x3 << 0)
794 #define RT5677_PDM2_EXE (0x1 << 3)
804 #define RT5677_IF1_ADC1_SWAP_MASK (0x3 << 6)
806 #define RT5677_IF1_ADC2_SWAP_MASK (0x3 << 4)
808 #define RT5677_IF1_ADC3_SWAP_MASK (0x3 << 2)
810 #define RT5677_IF1_ADC4_SWAP_MASK (0x3 << 0)
814 #define RT5677_IF1_ADC4_MASK (0x3 << 10)
816 #define RT5677_IF1_ADC3_MASK (0x3 << 8)
818 #define RT5677_IF1_ADC2_MASK (0x3 << 6)
820 #define RT5677_IF1_ADC1_MASK (0x3 << 4)
850 #define RT5677_IF2_ADC1_SWAP_MASK (0x3 << 6)
852 #define RT5677_IF2_ADC2_SWAP_MASK (0x3 << 4)
854 #define RT5677_IF2_ADC3_SWAP_MASK (0x3 << 2)
856 #define RT5677_IF2_ADC4_SWAP_MASK (0x3 << 0)
860 #define RT5677_IF2_ADC4_MASK (0x3 << 10)
862 #define RT5677_IF2_ADC3_MASK (0x3 << 8)
864 #define RT5677_IF2_ADC2_MASK (0x3 << 6)
866 #define RT5677_IF2_ADC1_MASK (0x3 << 4)
964 #define RT5677_DMIC_2L_LH_MASK (0x1 << 3)
965 #define RT5677_DMIC_2L_LH_SFT 3
966 #define RT5677_DMIC_2L_LH_FALLING (0x0 << 3)
967 #define RT5677_DMIC_2L_LH_RISING (0x1 << 3)
1000 #define RT5677_PWR_ADCFED1 (0x1 << 3)
1001 #define RT5677_PWR_ADCFED1_BIT 3
1034 #define RT5677_PWR_ADC_S4F (0x1 << 3)
1035 #define RT5677_PWR_ADC_S4F_BIT 3
1090 #define RT5677_PWR_IPTV (0x1 << 3)
1091 #define RT5677_PWR_IPTV_BIT 3
1112 #define RT5677_PWR_SR0 (0x1 << 3)
1113 #define RT5677_PWR_SR0_BIT 3
1134 #define RT5677_PWR_SR1_RDY (0x1 << 3)
1135 #define RT5677_PWR_SR1_RDY_BIT 3
1160 #define RT5677_PWR_SR2_ISO (0x1 << 3)
1161 #define RT5677_PWR_SR2_ISO_BIT 3
1169 /* I2S1/2/3/4 Audio Serial Data Port Control (0x6f 0x70 0x71 0x72) */
1174 #define RT5677_I2S_O_CP_MASK (0x3 << 10)
1179 #define RT5677_I2S_I_CP_MASK (0x3 << 8)
1188 #define RT5677_I2S_DL_MASK (0x3 << 2)
1193 #define RT5677_I2S_DL_8 (0x3 << 2)
1194 #define RT5677_I2S_DF_MASK (0x3 << 0)
1199 #define RT5677_I2S_DF_PCM_B (0x3 << 0)
1207 #define RT5677_I2S_PD1_4 (0x3 << 12)
1221 #define RT5677_I2S_PD2_4 (0x3 << 8)
1235 #define RT5677_I2S_PD3_4 (0x3 << 4)
1240 #define RT5677_I2S_BCLK_MS4_MASK (0x1 << 3)
1241 #define RT5677_I2S_BCLK_MS4_SFT 3
1242 #define RT5677_I2S_BCLK_MS4_32 (0x0 << 3)
1243 #define RT5677_I2S_BCLK_MS4_64 (0x1 << 3)
1249 #define RT5677_I2S_PD4_4 (0x3 << 0)
1261 #define RT5677_I2S_PD5_4 (0x3 << 12)
1271 #define RT5677_I2S_PD6_4 (0x3 << 8)
1281 #define RT5677_I2S_PD7_4 (0x3 << 4)
1291 #define RT5677_I2S_PD8_4 (0x3 << 0)
1297 /* Clock Tree Control 3 (0x75) */
1298 #define RT5677_DSP_ASRC_O_MASK (0x3 << 6)
1303 #define RT5677_DSP_ASRC_O_3_0 (0x3 << 6)
1304 #define RT5677_DSP_ASRC_I_MASK (0x3 << 4)
1309 #define RT5677_DSP_ASRC_I_3_0 (0x3 << 4)
1315 #define RT5677_DSP_BUS_PD_4 (0x3 << 0)
1343 #define RT5677_SCLK_SRC_MASK (0x3 << 14)
1348 #define RT5677_SCLK_SRC_SLIM (0x3 << 14)
1354 #define RT5677_PLL1_SRC_BCLK3 (0x3 << 11)
1366 #define RT5677_DAC_OSR_MASK (0x3 << 6)
1371 #define RT5677_ADC_OSR_MASK (0x3 << 4)
1387 #define RT5677_PLL2_SRC_BCLK3 (0x3 << 12)
1391 #define RT5677_DSP_ASRC_O_SRC (0x3 << 10)
1396 #define RT5677_DSP_ASRC_O_RCCLK (0x3 << 10)
1397 #define RT5677_DSP_ASRC_I_SRC (0x3 << 8)
1402 #define RT5677_DSP_ASRC_I_RCCLK (0x3 << 8)
1408 /* ASRC Control 3 (0x85) */
1459 #define RT5677_VAD_MIN_DUR_MASK (0x3 << 13)
1475 #define RT5677_VAD_FUNC_ENABLE (1 << 3)
1476 #define RT5677_VAD_FUNC_ENABLE_BIT 3
1485 #define RT5677_VAD_SRC_MASK (0x3 << 8)
1511 #define RT5677_SEL_SRC_OB01 (0x1 << 3)
1512 #define RT5677_SEL_SRC_OB01_SFT 3
1521 #define RT5677_SEL_GPIO_JD1_MASK (0x3 << 14)
1523 #define RT5677_SEL_GPIO_JD2_MASK (0x3 << 12)
1525 #define RT5677_SEL_GPIO_JD3_MASK (0x3 << 10)
1553 #define RT5677_STA_GPIO_JD3 (0x1 << 3)
1554 #define RT5677_STA_GPIO_JD3_SFT 3
1567 #define RT5677_GPIO4_STATUS_MASK (0x1 << 3)
1568 #define RT5677_GPIO4_STATUS_SFT 3
1590 /* GPIO Control 2 (0xc1) & 3 (0xc2) common bits */
1605 #define RT5677_IRQ_DEBOUNCE_SEL_MASK (0x3 << 3)
1606 #define RT5677_IRQ_DEBOUNCE_SEL_MCLK (0x0 << 3)
1607 #define RT5677_IRQ_DEBOUNCE_SEL_RC (0x1 << 3)
1608 #define RT5677_IRQ_DEBOUNCE_SEL_SLIM (0x2 << 3)
1633 #define RT5677_DSP_IB_7_L (0x1 << 3)
1634 #define RT5677_DSP_IB_7_L_SFT 3
1720 RT5677_DA_MONO3_L_FILTER = (0x1 << 3),
1756 /* jd1 can select 0 ~ 3 as OFF, GPIO1, GPIO2 and GPIO3 respectively */
1758 /* jd2 and jd3 can select 0 ~ 3 as
1763 /* Set MICBIAS1 VDD 1v8 or 3v3 */