soc/codecs/rt5631.h

216 #define RT5631_MIC1_BOOST_CTRL_30DB			(0x3 << 12)
228 #define RT5631_MIC2_BOOST_CTRL_30DB			(0x3 << 8)
244 #define RT5631_MICBIAS1_SHORT_CURR_DET_MASK		(0x3 << 4)
249 #define RT5631_MICBIAS2_VOLT_CTRL_MASK		(0x1 << 3)
250 #define RT5631_MICBIAS2_VOLT_CTRL_90P			(0x0 << 3)
251 #define RT5631_MICBIAS2_VOLT_CTRL_75P			(0x1 << 3)
257 #define RT5631_MICBIAS2_SHORT_CURR_DET_MASK		(0x3)
280 #define RT5631_DMIC_CLK_CTRL_MASK			(0x3 << 4)
322 #define RT5631_SPK_L_MUX_SEL_MASK			(0x3 << 14)
325 #define RT5631_SPK_L_MUX_SEL_DAC_L			(0x3 << 14)
328 #define RT5631_SPK_R_MUX_SEL_MASK			(0x3 << 10)
331 #define RT5631_SPK_R_MUX_SEL_DAC_R			(0x3 << 10)
334 #define RT5631_MONO_MUX_SEL_MASK			(0x3 << 6)
339 #define RT5631_HP_L_MUX_SEL_MASK			(0x1 << 3)
340 #define RT5631_HP_L_MUX_SEL_HPVOL_L			(0x0 << 3)
341 #define RT5631_HP_L_MUX_SEL_DAC_L			(0x1 << 3)
342 #define RT5631_HP_L_MUX_SEL_SHIFT			3
354 #define RT5631_SDP_ADC_CPS_SEL_MASK			(0x3 << 10)
359 #define RT5631_SDP_DAC_CPS_SEL_MASK			(0x3 << 8)
377 #define RT5631_SDP_I2S_DL_MASK				(0x3 << 2)
381 #define RT5631_SDP_I2S_DL_8				(0x3 << 2)
384 #define RT5631_SDP_I2S_DF_MASK				(0x3)
388 #define RT5631_SDP_I2S_DF_PCM_B			(0x3)
395 #define RT5631_I2S_PRE_DIV_8				(0x3 << 13)
403 #define RT5631_DAC_OSR_SEL_MASK			(0x3 << 10)
404 #define RT5631_DAC_OSR_SEL_128FS			(0x3 << 10)
405 #define RT5631_DAC_OSR_SEL_64FS			(0x3 << 10)
406 #define RT5631_DAC_OSR_SEL_32FS			(0x3 << 10)
407 #define RT5631_DAC_OSR_SEL_16FS			(0x3 << 10)
409 #define RT5631_ADC_OSR_SEL_MASK			(0x3 << 8)
410 #define RT5631_ADC_OSR_SEL_128FS			(0x3 << 8)
411 #define RT5631_ADC_OSR_SEL_64FS			(0x3 << 8)
412 #define RT5631_ADC_OSR_SEL_32FS			(0x3 << 8)
413 #define RT5631_ADC_OSR_SEL_16FS			(0x3 << 8)
455 #define RT5631_PWR_MICBIAS1_VOL			(0x1 << 3)
456 #define RT5631_PWR_MICBIAS1_VOL_BIT			3
464 /* Power managment addition 3(0x3C) */
483 #define RT5631_PWR_HP_L_AMP				(0x1 << 3)
484 #define RT5631_PWR_HP_L_AMP_BIT			3
521 #define RT5631_SPK_AMP_RATIO_CTRL_1_56		(0x3 << 12) /* 3.86DB */
531 #define RT5631_ADC_WIND_FILT_MASK			(0x3 << 4)
535 #define RT5631_ADC_WIND_FILT_EN			(0x1 << 3)
541 #define RT5631_ADC_WIND_CNR_FREQ_163_225_245 (0x3 << 0) /* 163/225/245 Hz */
548 #define RT5631_SYSCLK_SOUR_SEL_MASK			(0x3 << 14)
553 #define RT5631_PLLCLK_SOUR_SEL_MASK			(0x3 << 12)
567 #define RT5631_ADC_DATA_SEL_MASK			(0x3 << 14)
573 #define RT5631_ADC_DATA_SEL_STO			(0x3 << 14)
581 #define RT5631_GPIO_DMIC_FUN_SEL_MASK		(0x1 << 3)
582 #define RT5631_GPIO_DMIC_FUN_SEL_DIMC		(0x1 << 3)
583 #define RT5631_GPIO_DMIC_FUN_SEL_GPIO			(0x0 << 3)
607 #define RT5631_JD_USE_MASK				(0x3 << 14)
608 #define RT5631_JD_USE_JD2				(0x3 << 14)
633 #define RT5631_JD_AUX_1_EN				(0x1 << 3)
651 /* ALC CONTROL 3(0x66) */
652 #define RT5631_ALC_FUN_MASK				(0x3 << 14)
655 #define RT5631_ALC_ENA_ADC_PATH			(0x3 << 14)
671 /* 3D gain parameter */
672 #define RT5631_GAIN_3D_PARA_MASK		(0x3 << 6)
673 #define RT5631_GAIN_3D_PARA_1_00		(0x0 << 6) /* 3D gain 1.0 */
674 #define RT5631_GAIN_3D_PARA_1_50		(0x1 << 6) /* 3D gain 1.5 */
675 #define RT5631_GAIN_3D_PARA_2_00		(0x2 << 6) /* 3D gain 2.0 */
676 /* 3D ratio parameter */
677 #define RT5631_RATIO_3D_MASK			(0x3 << 4)
678 #define RT5631_RATIO_3D_0_0			(0x0 << 4) /* 3D ratio 0.0 */
679 #define RT5631_RATIO_3D_0_66			(0x1 << 4) /* 3D ratio 0.66 */
680 #define RT5631_RATIO_3D_1_0			(0x2 << 4) /* 3D ratio 1.0 */
682 #define RT5631_APF_FUN_SLE_MASK			(0x3 << 0)
683 #define RT5631_APF_FUN_SEL_48K				(0x3 << 0)
696 #define RT5631_EN_HW_EQ_BP3				(0x1 << 3)