Lines Matching +full:3 +full:x3
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
33 #define GOTGCTL_VBVALOVAL BIT(3)
57 #define GAHBCFG_HBSTLEN_INCR4 3
91 #define GUSBCFG_PHYIF16 BIT(3)
92 #define GUSBCFG_PHYIF8 (0 << 3)
107 #define GRSTCTL_CLOCK_SWITH_TIMER_VALUE_50 0x3
119 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
155 #define GINTSTS_SOF BIT(3)
169 #define GRXSTS_PKTSTS_OUTDONE 3
170 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
177 #define GRXSTS_DPID_MASK (0x3 << 15)
205 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
232 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
234 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
243 #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
248 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
249 #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
254 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
256 #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
257 #define GHWCFG2_ARCHITECTURE_SHIFT 3
266 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
303 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
334 #define GLPMCFG_COREL1RES_MASK (0x3 << 13)
354 #define GPWRDN_LINESTATE_MASK (0x3 << 19)
371 #define GPWRDN_PWRDNCLMP BIT(3)
383 #define ADPCTL_AR_MASK (0x3 << 27)
397 #define ADPCTL_PRB_PER_MASK (0x3 << 4)
399 #define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
401 #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
439 #define DCFG_PERFRINT_MASK (0x3 << 11)
441 #define DCFG_PERFRINT_LIMIT 0x3
448 #define DCFG_DEVSPD_MASK (0x3 << 0)
453 #define DCFG_DEVSPD_FS48 3
464 #define DCTL_GOUTNAKSTS BIT(3)
474 #define DSTS_ERRATICERR BIT(3)
475 #define DSTS_ENUMSPD_MASK (0x3 << 1)
480 #define DSTS_ENUMSPD_FS48 3
491 #define DIEPMSK_TIMEOUTMSK BIT(3)
501 #define DOEPMSK_SETUPMSK BIT(3)
532 #define D0EPCTL_MPS_MASK (0x3 << 0)
537 #define D0EPCTL_MPS_8 3
553 #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
557 #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
589 #define DXEPINT_TIMEOUT BIT(3)
590 #define DXEPINT_SETUP BIT(3)
596 #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
598 #define DIEPTSIZ0_PKTCNT_LIMIT 0x3
606 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
608 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3
616 #define DXEPTSIZ_MC_MASK (0x3 << 29)
618 #define DXEPTSIZ_MC_LIMIT 0x3
638 #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
640 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
645 #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
648 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
659 #define PCGCTL_RSTPDWNMODULE BIT(3)
665 #define PCGCCTL1_TIMER (0x3 << 1)
675 #define HCFG_FRLISTEN_MASK (0x3 << 24)
683 #define HCFG_FRLISTEN_64 (3 << 24)
690 #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
712 #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
725 #define HPRT0_SPD_MASK (0x3 << 17)
733 #define HPRT0_LNSTS_MASK (0x3 << 10)
740 #define HPRT0_ENACHG BIT(3)
751 #define HCCHAR_MULTICNT_MASK (0x3 << 20)
753 #define HCCHAR_EPTYPE_MASK (0x3 << 18)
765 #define HCSPLT_XACTPOS_MASK (0x3 << 14)
770 #define HCSPLT_XACTPOS_ALL 3
789 #define HCINTMSK_STALL BIT(3)
796 #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
801 #define TSIZ_SC_MC_PID_MDATA 3
802 #define TSIZ_SC_MC_PID_SETUP 3
836 #define HOST_DMA_STS_MASK (0x3 << 28)
853 #define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
858 #define DEV_DMA_BUFF_STS_HBUSY 3
859 #define DEV_DMA_STS_MASK (0x3 << 28)
863 #define DEV_DMA_STS_BUFF_ERR 3
869 #define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
874 #define DEV_DMA_ISOC_PID_MDATA 3