Lines Matching +full:3 +full:x3
218 #define RT5616_ADC_L_BST_MASK (0x3 << 14)
220 #define RT5616_ADC_R_BST_MASK (0x3 << 12)
222 #define RT5616_ADC_COMP_MASK (0x3 << 10)
278 #define RT5616_STO_DD_R2_VOL_MASK (0x1 << 3)
279 #define RT5616_STO_DD_R2_VOL_SFT 3
314 #define RT5616_DAC_L2_SEL_MASK (0x3 << 14)
319 #define RT5616_DAC_L2_SEL_BASS (0x3 << 14)
320 #define RT5616_DAC_R2_SEL_MASK (0x3 << 12)
333 #define RT5616_RXDC_SEL_MASK (0x3 << 8)
338 #define RT5616_RXDC_SEL_SWAP (0x3 << 8)
339 #define RT5616_RXDP_SEL_MASK (0x3 << 6)
344 #define RT5616_RXDP_SEL_SWAP (0x3 << 6)
345 #define RT5616_TXDC_SEL_MASK (0x3 << 4)
350 #define RT5616_TXDC_SEL_SWAP (0x3 << 4)
351 #define RT5616_TXDP_SEL_MASK (0x3 << 2)
356 #define RT5616_TRXDP_SEL_SWAP (0x3 << 2)
377 #define RT5616_M_BST3_RM_L (0x1 << 3)
378 #define RT5616_M_BST3_RM_L_SFT 3
405 #define RT5616_M_BST3_RM_R (0x1 << 3)
406 #define RT5616_M_BST3_RM_R_SFT 3
423 #define RT5616_G_RM_L_SM_L_MASK (0x3 << 14)
425 #define RT5616_G_IN_L_SM_L_MASK (0x3 << 12)
427 #define RT5616_G_DAC_L1_SM_L_MASK (0x3 << 10)
429 #define RT5616_G_DAC_L2_SM_L_MASK (0x3 << 8)
431 #define RT5616_G_OM_L_SM_L_MASK (0x3 << 6)
437 #define RT5616_M_DAC_L1_SM_L (0x1 << 3)
438 #define RT5616_M_DAC_L1_SM_L_SFT 3
445 #define RT5616_G_RM_R_SM_R_MASK (0x3 << 14)
447 #define RT5616_G_IN_R_SM_R_MASK (0x3 << 12)
449 #define RT5616_G_DAC_R1_SM_R_MASK (0x3 << 10)
451 #define RT5616_G_DAC_R2_SM_R_MASK (0x3 << 8)
453 #define RT5616_G_OM_R_SM_R_MASK (0x3 << 6)
459 #define RT5616_M_DAC_R1_SM_R (0x1 << 3)
460 #define RT5616_M_DAC_R1_SM_R_SFT 3
520 /* Output Left Mixer Control 3 (0x4f) */
529 #define RT5616_M_RM_L_OM_L (0x1 << 3)
530 #define RT5616_M_RM_L_OM_L_SFT 3
550 /* Output Right Mixer Control 3 (0x52) */
559 #define RT5616_M_RM_R_OM_R (0x1 << 3)
560 #define RT5616_M_RM_R_OM_R_SFT 3
615 #define RT5616_PWR_FV2 (0x1 << 3)
616 #define RT5616_PWR_FV2_BIT 3
619 #define RT5616_PWR_LDO_DVO_MASK (0x3)
623 #define RT5616_PWR_LDO_DVO_1_3V 3
638 #define RT5616_PWR_BST3_OP2 (0x1 << 3)
639 #define RT5616_PWR_BST3_OP2_BIT 3
675 /* I2S1/2/3 Audio Serial Data Port Control (0x70 0x71) */
680 #define RT5616_I2S_O_CP_MASK (0x3 << 10)
685 #define RT5616_I2S_I_CP_MASK (0x3 << 8)
694 #define RT5616_I2S_DL_MASK (0x3 << 2)
699 #define RT5616_I2S_DL_8 (0x3 << 2)
700 #define RT5616_I2S_DF_MASK (0x3)
705 #define RT5616_I2S_DF_PCM_B (0x3)
713 #define RT5616_I2S_PD1_4 (0x3 << 12)
719 #define RT5616_DAC_OSR_MASK (0x3 << 2)
724 #define RT5616_DAC_OSR_128_3 (0x3 << 2)
725 #define RT5616_ADC_OSR_MASK (0x3)
730 #define RT5616_ADC_OSR_128_3 (0x3)
747 #define RT5616_TDM_CH_NUM_SEL_MASK (0x3 << 12)
752 #define RT5616_TDM_CH_NUM_SEL_8 (0x3 << 12)
753 #define RT5616_TDM_CH_LEN_SEL_MASK (0x3 << 10)
758 #define RT5616_TDM_CH_LEN_SEL_32 (0x3 << 10)
767 #define RT5616_TDM_I2S_CH2_SEL_MASK (0x3 << 6)
772 #define RT5616_TDM_I2S_CH2_SEL_RR (0x3 << 6)
773 #define RT5616_TDM_I2S_CH4_SEL_MASK (0x3 << 4)
778 #define RT5616_TDM_I2S_CH4_SEL_RR (0x3 << 4)
779 #define RT5616_TDM_I2S_CH6_SEL_MASK (0x3 << 2)
784 #define RT5616_TDM_I2S_CH6_SEL_RR (0x3 << 2)
785 #define RT5616_TDM_I2S_CH8_SEL_MASK (0x3)
790 #define RT5616_TDM_I2S_CH8_SEL_RR (0x3)
829 #define RT5616_SCLK_SRC_MASK (0x3 << 14)
833 #define RT5616_PLL1_SRC_MASK (0x3 << 12)
838 #define RT5616_PLL1_PD_MASK (0x1 << 3)
839 #define RT5616_PLL1_PD_SFT 3
840 #define RT5616_PLL1_PD_1 (0x0 << 3)
841 #define RT5616_PLL1_PD_2 (0x1 << 3)
899 #define RT5616_I2S2_R_D_MASK (0x1 << 3)
900 #define RT5616_I2S2_R_D_SFT 3
901 #define RT5616_I2S2_R_D_DIS (0x0 << 3)
902 #define RT5616_I2S2_R_D_EN (0x1 << 3)
903 #define RT5616_PRE_SCLK_MASK (0x3)
909 /* PLL tracking mode 3 (0x85) */
914 #define RT5616_G_ASRC_LP_MASK (0x1 << 3)
915 #define RT5616_G_ASRC_LP_SFT 3
920 #define RT5616_FTK_PH_DET_MASK (0x3)
925 #define RT5616_FTK_PH_DET_DIV8 (0x3)
944 #define RT5616_HP_OC_TH_MASK (0x3 << 8)
949 #define RT5616_HP_OC_TH_135 (0x3 << 8)
980 #define RT5616_HP_CP_MASK (0x1 << 3)
981 #define RT5616_HP_CP_SFT 3
982 #define RT5616_HP_CP_PD (0x0 << 3)
983 #define RT5616_HP_CP_PU (0x1 << 3)
1014 #define RT5616_MRES_MASK (0x3 << 8)
1019 #define RT5616_MRES_45MO (0x3 << 8)
1028 #define RT5616_DP_TH_MASK (0x3 << 4)
1031 /* Depop Mode Control 3 (0x90) */
1043 #define RT5616_CP_FQ_12_KHZ 3
1058 #define RT5616_PM_HP_MASK (0x3 << 8)
1063 #define RT5616_IB_HP_MASK (0x3 << 6)
1068 #define RT5616_IB_HP_1IL (0x3 << 6)
1083 #define RT5616_MIC1_OVTH_MASK (0x3 << 9)
1104 #define RT5616_JD_MODE_SEL_MASK (0x3 << 8)
1111 #define RT5616_JD_M_PU (0x1 << 3)
1112 #define RT5616_JD_M_PU_SFT 3
1115 #define RT5616_JD_M_MODE_SEL_MASK (0x3)
1136 #define RT5616_EQ_DITH_MASK (0x3 << 8)
1141 #define RT5616_EQ_DITH_LSB_2 (0x3 << 8)
1150 #define RT5616_EQ_STA_BP3 (0x1 << 3)
1151 #define RT5616_EQ_STA_BP3_BIT 3
1180 #define RT5616_EQ_BPF3_MASK (0x1 << 3)
1181 #define RT5616_EQ_BPF3_SFT 3
1182 #define RT5616_EQ_BPF3_DIS (0x0 << 3)
1183 #define RT5616_EQ_BPF3_EN (0x1 << 3)
1221 #define RT5616_DRC_AGC_R_192K (0x3 << 5)
1235 #define RT5616_DRC_AGC_CPR_MASK (0x3 << 5)
1240 #define RT5616_DRC_AGC_CPR_1_4 (0x3 << 5)
1244 /* DRC/AGC Control 3 (0xb6) */
1266 #define RT5616_JD_GPIO3 (0x3 << 13)
1294 #define RT5616_JD_LO_MASK (0x1 << 3)
1295 #define RT5616_JD_LO_SFT 3
1296 #define RT5616_JD_LO_DIS (0x0 << 3)
1297 #define RT5616_JD_LO_EN (0x1 << 3)
1309 #define RT5616_JD_TRG_SEL_JD2 (0x3 << 9)
1343 #define RT5616_JD2_IRQ_EN (0x1 << 3)
1344 #define RT5616_JD2_IRQ_EN_SFT 3
1364 #define RT5616_MB1_OC_CLR (0x1 << 3)
1365 #define RT5616_MB1_OC_CLR_SFT 3
1428 #define RT5616_GPIO_PDM_SEL_MASK (0x1 << 3)
1429 #define RT5616_GPIO_PDM_SEL_SFT 3
1430 #define RT5616_GPIO_PDM_SEL_GPIO (0x0 << 3)
1431 #define RT5616_GPIO_PDM_SEL_PDM (0x1 << 3)
1478 #define RT5616_GP2_P_MASK (0x1 << 3)
1479 #define RT5616_GP2_P_SFT 3
1480 #define RT5616_GP2_P_NOR (0x0 << 3)
1481 #define RT5616_GP2_P_INV (0x1 << 3)
1495 /* GPIO Control 3 (0xc2) */
1516 #define RT5616_GP7_P_MASK (0x1 << 3)
1517 #define RT5616_GP7_P_SFT 3
1518 #define RT5616_GP7_P_NOR (0x0 << 3)
1519 #define RT5616_GP7_P_INV (0x1 << 3)
1553 #define RT5616_BB_CT_D (0x3 << 12)
1595 /* 3D HP Control 1 (0xd2) */
1608 #define RT5616_3D_1F_MIX_MASK (0x3 << 11)
1632 #define RT5616_ZD_T_MASK (0x3 << 6)
1634 #define RT5616_ZD_F_MASK (0x3 << 4)
1639 #define RT5616_ZD_F_UN (0x3 << 4)
1670 #define RT5616_CAL_MASK (0x1 << 3)
1671 #define RT5616_CAL_SFT 3
1672 #define RT5616_CAL_DIS (0x0 << 3)
1673 #define RT5616_CAL_EN (0x1 << 3)
1678 #define RT5616_CAL_P_MASK (0x3)
1725 #define RT5616_CLK_DET_EN (0x1 << 3)
1726 #define RT5616_CLK_DET_EN_SFT 3
1733 /* 3D Speaker Control (0x63) */
1738 #define RT5616_3D_SPK_M_MASK (0x3 << 13)
1757 /* Wind Noise Detection Control 3 (0x6e) */
1783 #define RT5616_DP_ATT_MASK (0x3 << 14)