Lines Matching +full:3 +full:x3

105 #define RT1318_PLLIN_MCLK			(0x3 << 4)
114 #define RT1318_SYSCLK_PLL2B			(0x3 << 0)
120 #define RT1318_DIV_AP_MASK			(0x3 << 4)
125 #define RT1318_DIV_AP_DIV8			(0x3 << 4)
126 #define RT1318_DIV_DAMOD_MASK			(0x3 << 0)
131 #define RT1318_DIV_DAMOD_DIV8			(0x3 << 0)
132 /* Clock-3  (0xC004) */
138 #define RT1318_AD_STO1_DIV8			(0x3 << 4)
145 #define RT1318_AD_STO2_DIV8			(0x3 << 0)
154 #define RT1318_AD_ANA_STO1_DIV8			(0x3 << 4)
160 #define RT1318_AD_ANA_STO2_DIV8			(0x3 << 0)
164 #define RT1318_DIV_FIFO_IN_MASK			(0x3 << 4)
169 #define RT1318_DIV_FIFO_IN_DIV8			(0x3 << 4)
170 #define RT1318_DIV_FIFO_OUT_MASK		(0x3 << 0)
174 #define RT1318_DIV_FIFO_OUT_DIV8		(0x3 << 0)
177 #define RT1318_DIV_NLMS_MASK			(0x3 << 6)
182 #define RT1318_DIV_NLMS_DIV8			(0x3 << 6)
183 #define RT1318_DIV_AD_MONO_MASK			(0x7 << 3)
184 #define RT1318_DIV_AD_MONO_SFT			3
185 #define RT1318_DIV_AD_MONO_DIV1			(0x0 << 3)
186 #define RT1318_DIV_AD_MONO_DIV2			(0x1 << 3)
187 #define RT1318_DIV_AD_MONO_DIV4			(0x2 << 3)
188 #define RT1318_DIV_AD_MONO_DIV8			(0x3 << 3)
189 #define RT1318_DIV_AD_MONO_DIV16		(0x4 << 3)
195 #define RT1318_DIV_POST_G_DIV8			(0x3 << 0)
203 #define RT1318_SRCIN_IN_SEL_MASK		(0x3 << 6)
207 #define RT1318_SRCIN_IN_16K			(0x3 << 6)
208 #define RT1318_SRCIN_F12288_MASK		(0x3 << 4)
212 #define RT1318_SRCIN_TCON8			(0x3 << 4)
213 #define RT1318_SRCIN_DACLK_MASK			(0x3 << 2)
217 #define RT1318_DACLK_TCON8			(0x3 << 2)
238 #define RT1318_FMT_PCM_B_R			(0x3 << 0)
243 #define RT1318_I2S_CH_TX_MASK			(0x3 << 6)
247 #define RT1318_I2S_CH_TX_8CH			(0x3 << 6)
248 #define RT1318_I2S_CH_RX_MASK			(0x3 << 4)
252 #define RT1318_I2S_CH_RX_8CH			(0x3 << 4)
258 #define RT1318_I2S_DL_32			0x3
260 /* TDM CTRL 3  (0xf902) */
266 #define RT1318_I2S_TX_CHL_32			(0x3 << 4)
273 #define RT1318_I2S_RX_CHL_32			(0x3 << 0)