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/linux-6.12.1/drivers/firmware/broadcom/
Dbcm47xx_sprom.c76 if (err < 0) \
78 err = kstrto ## type(strim(buf), 0, &var); \
104 if (err < 0) in NVRAM_READ_VAL()
106 err = kstrtou32(strim(buf), 0, &val); in NVRAM_READ_VAL()
112 *val_lo = (val & 0x0000FFFFU); in NVRAM_READ_VAL()
113 *val_hi = (val & 0xFFFF0000U) >> 16; in NVRAM_READ_VAL()
125 if (err < 0) in nvram_read_leddc()
127 err = kstrtou32(strim(buf), 0, &val); in nvram_read_leddc()
134 if (val == 0xffff || val == 0xffffffff) in nvram_read_leddc()
137 *leddc_on_time = val & 0xff; in nvram_read_leddc()
[all …]
/linux-6.12.1/drivers/message/fusion/lsi/
Dmpi_init.h88 U8 LUN[8]; /* 0Ch */
100 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01)
101 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00)
102 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01)
104 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02)
105 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00)
106 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02)
108 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04)
112 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
113 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
[all …]
/linux-6.12.1/drivers/gpu/drm/etnaviv/
Dstate.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define VARYING_COMPONENT_USE_UNUSED 0x00000000
49 #define VARYING_COMPONENT_USE_USED 0x00000001
50 #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002
51 #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003
52 #define FE_DATA_TYPE_BYTE 0x00000000
53 #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001
54 #define FE_DATA_TYPE_SHORT 0x00000002
55 #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
[all …]
/linux-6.12.1/drivers/video/fbdev/geode/
Ddisplay_gx1.h21 #define CONFIG_CCR3 0xc3
22 # define CONFIG_CCR3_MAPEN 0x10
23 #define CONFIG_GCR 0xb8
27 #define MC_BANK_CFG 0x08
28 # define MC_BCFG_DIMM0_SZ_MASK 0x00000700
29 # define MC_BCFG_DIMM0_PG_SZ_MASK 0x00000070
30 # define MC_BCFG_DIMM0_PG_SZ_NO_DIMM 0x00000070
32 #define MC_GBASE_ADD 0x14
33 # define MC_GADD_GBADD_MASK 0x000003ff
37 #define DC_PAL_ADDRESS 0x70
[all …]
/linux-6.12.1/drivers/gpu/drm/nouveau/include/nvhw/class/
Dcl837d.h28 #define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0…
29 #define NV837D_SOR_SET_CONTROL_OWNER 3:0
30 #define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000)
31 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001)
32 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002)
34 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000)
35 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001)
36 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002)
37 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003)
39 #define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000)
[all …]
Dcla0b5.h27 #define NVA0B5_SET_SRC_PHYS_MODE (0x00000260)
28 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET 1:0
29 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
30 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
31 #define NVA0B5_SET_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
32 #define NVA0B5_SET_DST_PHYS_MODE (0x00000264)
33 #define NVA0B5_SET_DST_PHYS_MODE_TARGET 1:0
34 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_LOCAL_FB (0x00000000)
35 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM (0x00000001)
36 #define NVA0B5_SET_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM (0x00000002)
[all …]
/linux-6.12.1/arch/mips/include/asm/mach-rc32434/
Dddr.h49 #define DDR0_PHYS_ADDR 0x18018000
52 #define DDR_MASK 0xffff0000
58 #define RC32434_DDR0_ATA_MSK 0x000000E0
60 #define RC32434_DDR0_DBW_MSK 0x00000100
62 #define RC32434_DDR0_WR_MSK 0x00000600
64 #define RC32434_DDR0_PS_MSK 0x00001800
66 #define RC32434_DDR0_DTYPE_MSK 0x0000e000
68 #define RC32434_DDR0_RFC_MSK 0x000f0000
70 #define RC32434_DDR0_RP_MSK 0x00300000
72 #define RC32434_DDR0_AP_MSK 0x00400000
[all …]
/linux-6.12.1/drivers/scsi/mpi3mr/mpi/
Dmpi30_transport.h20 #define MPI3_VERSION_MINOR (0)
22 #define MPI3_VERSION_DEV (0)
23 #define MPI3_DEVHANDLE_INVALID (0xffff)
73 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000)
74 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004)
75 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xff000000)
77 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001)
78 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014)
79 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00f00000)
81 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000f0000)
[all …]
/linux-6.12.1/drivers/net/wireless/ath/ath9k/
Dreg_aic.h20 #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0)
21 #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4)
22 #define AR_PHY_AIC_CTRL_2_B0 (AR_SM_BASE + 0x4b8)
23 #define AR_PHY_AIC_CTRL_3_B0 (AR_SM_BASE + 0x4bc)
24 #define AR_PHY_AIC_CTRL_4_B0 (AR_SM_BASE + 0x4c0)
26 #define AR_PHY_AIC_STAT_0_B0 (AR_SM_BASE + 0x4c4)
27 #define AR_PHY_AIC_STAT_1_B0 (AR_SM_BASE + 0x4c8)
28 #define AR_PHY_AIC_STAT_2_B0 (AR_SM_BASE + 0x4cc)
30 #define AR_PHY_AIC_CTRL_0_B1 (AR_SM1_BASE + 0x4b0)
31 #define AR_PHY_AIC_CTRL_1_B1 (AR_SM1_BASE + 0x4b4)
[all …]
/linux-6.12.1/include/linux/bcma/
Dbcma_regs.h7 #define BCMA_CLKCTLST 0x01E0 /* Clock control and status */
8 #define BCMA_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
9 #define BCMA_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
10 #define BCMA_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
11 #define BCMA_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
12 #define BCMA_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
13 #define BCMA_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
14 #define BCMA_CLKCTLST_HQCLKREQ 0x00000040 /* HQ Clock */
15 #define BCMA_CLKCTLST_EXTRESREQ 0x00000700 /* Mask of external resource requests */
17 #define BCMA_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
[all …]
Dbcma_driver_chipcommon.h10 #define BCMA_CC_ID 0x0000
11 #define BCMA_CC_ID_ID 0x0000FFFF
12 #define BCMA_CC_ID_ID_SHIFT 0
13 #define BCMA_CC_ID_REV 0x000F0000
15 #define BCMA_CC_ID_PKG 0x00F00000
17 #define BCMA_CC_ID_NRCORES 0x0F000000
19 #define BCMA_CC_ID_TYPE 0xF0000000
21 #define BCMA_CC_CAP 0x0004 /* Capabilities */
22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
[all …]
/linux-6.12.1/arch/mips/kernel/
Dirq_txx9.c38 #define TXx9_IRCER_ICE 0x00000001
41 #define TXx9_IRCR_LOW 0x00000000
42 #define TXx9_IRCR_HIGH 0x00000001
43 #define TXx9_IRCR_DOWN 0x00000002
44 #define TXx9_IRCR_UP 0x00000003
45 #define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002)
48 #define TXx9_IRSCR_EIClrE 0x00000100
49 #define TXx9_IRSCR_EIClr_MASK 0x0000000f
52 #define TXx9_IRCSR_IF 0x00010000
53 #define TXx9_IRCSR_ILV_MASK 0x00000700
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-vi.yaml15 pattern: "^vi@[0-9a-f]+$"
83 port@0:
89 "^csi@[0-9a-f]+$":
125 #size-cells = <0>;
128 reg = <0x48>;
141 reg = <0x54080000 0x00040000>;
151 #size-cells = <0>;
152 port@0 {
153 reg = <0>;
169 #size-cells = <0>;
[all …]
/linux-6.12.1/drivers/staging/rtl8192e/rtl8192e/
Dtable.c10 0x800, 0x00000000,
11 0x804, 0x00000001,
12 0x808, 0x0000fc00,
13 0x80c, 0x0000001c,
14 0x810, 0x801010aa,
15 0x814, 0x008514d0,
16 0x818, 0x00000040,
17 0x81c, 0x00000000,
18 0x820, 0x00000004,
19 0x824, 0x00690000,
[all …]
/linux-6.12.1/arch/sparc/include/asm/
Decc.h12 /* These registers are accessed through the SRMMU passthrough ASI 0x20 */
13 #define ECC_ENABLE 0x00000000 /* ECC enable register */
14 #define ECC_FSTATUS 0x00000008 /* ECC fault status register */
15 #define ECC_FADDR 0x00000010 /* ECC fault address register */
16 #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
17 #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
18 #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
25 * 31 5 4 3 2 1 0
27 * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
28 * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
[all …]
/linux-6.12.1/drivers/media/pci/intel/ipu6/
Dipu6-isys-mcd-phy.c22 #define CSI_REG_HUB_GPREG_PHY_CTL(id) (CSI_REG_BASE + 0x18008 + (id) * 0x8)
24 #define CSI_REG_HUB_GPREG_PHY_CTL_PWR_EN BIT(0)
25 #define CSI_REG_HUB_GPREG_PHY_STATUS(id) (CSI_REG_BASE + 0x1800c + (id) * 0x8)
26 #define CSI_REG_HUB_GPREG_PHY_POWER_ACK BIT(0)
35 #define IPU6_ISYS_MCD_PHY_BASE(i) (0x10000 + (i) * 0x4000)
41 * CSI port 0, 2 (4, 6) can support max 4 data lanes.
88 * Left : port0 - PPI range {0, 1, 2, 3, 4}
92 * Left: port0 - PPI range {0, 1, 2, 3, 4}
96 * Left: port0 - PPI range {0, 1, 2}, port1 - PPI range {3, 4, 5}
100 * Left : port0 - PPI range {0, 1, 2}, port1 - PPI range {3, 4, 5}
[all …]
/linux-6.12.1/drivers/net/wireless/ralink/rt2x00/
Drt73usb.h20 #define RF5226 0x0001
21 #define RF2528 0x0002
22 #define RF5225 0x0003
23 #define RF2527 0x0004
34 #define CSR_REG_BASE 0x3000
35 #define CSR_REG_SIZE 0x04b0
36 #define EEPROM_BASE 0x0000
37 #define EEPROM_SIZE 0x0100
38 #define BBP_BASE 0x0000
39 #define BBP_SIZE 0x0080
[all …]
/linux-6.12.1/drivers/media/platform/imagination/
De5010-mmu-regs.h14 #define MMU_MMU_DIR_BASE_ADDR_OFFSET (0x0020)
18 #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_MASK (0xFFFFFFFF)
19 #define MMU_MMU_DIR_BASE_ADDR_MMU_DIR_BASE_ADDR_SHIFT (0)
21 #define MMU_MMU_TILE_CFG_OFFSET (0x0040)
25 #define MMU_MMU_TILE_CFG_TILE_128INTERLEAVE_MASK (0x00000010)
28 #define MMU_MMU_TILE_CFG_TILE_ENABLE_MASK (0x00000008)
31 #define MMU_MMU_TILE_CFG_TILE_STRIDE_MASK (0x00000007)
32 #define MMU_MMU_TILE_CFG_TILE_STRIDE_SHIFT (0)
34 #define MMU_MMU_TILE_MIN_ADDR_OFFSET (0x0050)
38 #define MMU_MMU_TILE_MIN_ADDR_TILE_MIN_ADDR_MASK (0xFFFFFFFF)
[all …]
/linux-6.12.1/include/sound/
Dcs35l56.h17 #define CS35L56_DEVID 0x0000000
18 #define CS35L56_REVID 0x0000004
19 #define CS35L56_RELID 0x000000C
20 #define CS35L56_OTPID 0x0000010
21 #define CS35L56_SFT_RESET 0x0000020
22 #define CS35L56_GLOBAL_ENABLES 0x0002014
23 #define CS35L56_BLOCK_ENABLES 0x0002018
24 #define CS35L56_BLOCK_ENABLES2 0x000201C
25 #define CS35L56_REFCLK_INPUT 0x0002C04
26 #define CS35L56_GLOBAL_SAMPLE_RATE 0x0002C0C
[all …]
/linux-6.12.1/arch/mips/include/asm/mips-boards/
Dmsc01_pci.h19 #define MSC01_PCI_ID_OFS 0x0000
20 #define MSC01_PCI_SC2PMBASL_OFS 0x0208
21 #define MSC01_PCI_SC2PMMSKL_OFS 0x0218
22 #define MSC01_PCI_SC2PMMAPL_OFS 0x0228
23 #define MSC01_PCI_SC2PIOBASL_OFS 0x0248
24 #define MSC01_PCI_SC2PIOMSKL_OFS 0x0258
25 #define MSC01_PCI_SC2PIOMAPL_OFS 0x0268
26 #define MSC01_PCI_P2SCMSKL_OFS 0x0308
27 #define MSC01_PCI_P2SCMAPL_OFS 0x0318
28 #define MSC01_PCI_INTCFG_OFS 0x0600
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Daiutils.h29 #define SI_CORE_SIZE 0x1000
38 #define SI_PCI_DMA_SZ 0x40000000
41 #define SI_PCIE_DMA_H32 0x80000000
44 #define SI_CC_IDX 0
52 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
55 #define CCS_FORCEALP 0x00000001 /* force ALP request */
56 #define CCS_FORCEHT 0x00000002 /* force HT request */
57 #define CCS_FORCEILP 0x00000004 /* force ILP request */
58 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
59 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
[all …]
Drate.h52 #define MCS_TXS_MASK 0xc0 /* num tx streams - 1 bit mask */
75 #define BRCMS_RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */
87 #define RSPEC_RATE_MASK 0x0000007F
89 #define RSPEC_MIMORATE 0x08000000
91 #define RSPEC_BW_MASK 0x00000700
95 #define RSPEC_STF_MASK 0x00003800
99 #define RSPEC_CT_MASK 0x0000C000
103 #define RSPEC_STC_MASK 0x00300000
107 #define RSPEC_LDPC_CODING 0x00400000
109 #define RSPEC_SHORT_GI 0x00800000
[all …]
/linux-6.12.1/drivers/firewire/
Dphy-packet-definitions.h10 #define PACKET_IDENTIFIER_MASK 0xc0000000
24 #define PHY_PACKET_PACKET_IDENTIFIER_PHY_CONFIG 0
26 #define PHY_CONFIG_ROOT_ID_MASK 0x3f000000
28 #define PHY_CONFIG_FORCE_ROOT_NODE_MASK 0x00800000
30 #define PHY_CONFIG_GAP_COUNT_OPTIMIZATION_MASK 0x00400000
32 #define PHY_CONFIG_GAP_COUNT_MASK 0x003f0000
81 #define SELF_ID_PHY_ID_MASK 0x3f000000
83 #define SELF_ID_EXTENDED_MASK 0x00800000
85 #define SELF_ID_MORE_PACKETS_MASK 0x00000001
86 #define SELF_ID_MORE_PACKETS_SHIFT 0
[all …]
/linux-6.12.1/arch/mips/ath25/
Dar5312_regs.h17 #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
18 #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
19 #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
20 #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
21 #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
26 #define AR5312_MISC_IRQ_TIMER 0
41 * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
44 #define AR5312_WLAN0_BASE 0x18000000
45 #define AR5312_ENET0_BASE 0x18100000
46 #define AR5312_ENET1_BASE 0x18200000
[all …]
/linux-6.12.1/drivers/atm/
Dmidway.h19 #define MAP_MAX_SIZE 0x00400000 /* memory window for max config */
20 #define EPROM_SIZE 0x00010000
21 #define MEM_VALID 0xffc00000 /* mask base address with this */
22 #define PHY_BASE 0x00020000 /* offset of PHY register are */
23 #define REG_BASE 0x00040000 /* offset of Midway register area */
24 #define RAM_BASE 0x00200000 /* offset of RAM area */
25 #define RAM_INCREMENT 0x00020000 /* probe for RAM every 128kB */
50 #define MID_RES_ID_MCON 0x00 /* Midway Reset/ID */
52 #define MID_ID 0xf0000000 /* Midway version */
54 #define MID_MOTHER_ID 0x00000700 /* mother board id */
[all …]

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