Lines Matching +full:0 +full:x00000700

12 /* These registers are accessed through the SRMMU passthrough ASI 0x20 */
13 #define ECC_ENABLE 0x00000000 /* ECC enable register */
14 #define ECC_FSTATUS 0x00000008 /* ECC fault status register */
15 #define ECC_FADDR 0x00000010 /* ECC fault address register */
16 #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
17 #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
18 #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
25 * 31 5 4 3 2 1 0
27 * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
28 * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
29 * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on
30 * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on
33 #define ECC_MBAE_SBUS 0x00000010
34 #define ECC_MBAE_MOD3 0x00000008
35 #define ECC_MBAE_MOD2 0x00000004
36 #define ECC_MBAE_MOD1 0x00000002
43 * 31 2 1 0
45 * ECHECK: Enable ECC checking. 0=off 1=on
46 * EINT: Enable Interrupts for correctable errors. 0=off 1=on
48 #define ECC_FCR_CHECK 0x00000002
49 #define ECC_FCR_INTENAB 0x00000001
56 * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0
59 * S: Supervisor/Privileged access? 0=no 1=yes
63 * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot
65 * AT: Did this fault happen during an atomic instruction? 0=no
71 * 0=no 1=yes
76 #define ECC_FADDR0_MIDMASK 0xf0000000
77 #define ECC_FADDR0_S 0x08000000
78 #define ECC_FADDR0_VADDR 0x003fc000
79 #define ECC_FADDR0_BMODE 0x00002000
80 #define ECC_FADDR0_ATOMIC 0x00001000
81 #define ECC_FADDR0_CACHE 0x00000800
82 #define ECC_FADDR0_SIZE 0x00000700
83 #define ECC_FADDR0_TYPE 0x000000f0
84 #define ECC_FADDR0_PADDR 0x0000000f
89 * | Physical Address 31-0 |
91 * 31 0
102 * 31-18 17 16 15-8 7-4 3 2 1 0
104 * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
105 * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
108 * UNC: Uncorrectable error. 0=no 1=yes
109 * TIMEO: Timeout occurred. 0=no 1=yes
110 * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
111 * C: Correctable error? 0=no 1=yes
114 #define ECC_FSR_C2ERR 0x00020000
115 #define ECC_FSR_MULT 0x00010000
116 #define ECC_FSR_SYND 0x0000ff00
117 #define ECC_FSR_DWORD 0x000000f0
118 #define ECC_FSR_UNC 0x00000008
119 #define ECC_FSR_TIMEO 0x00000004
120 #define ECC_FSR_BADSLOT 0x00000002
121 #define ECC_FSR_C 0x00000001