mips/kernel/irq_txx9.c

38 #define TXx9_IRCER_ICE	0x00000001
41 #define TXx9_IRCR_LOW	0x00000000
42 #define TXx9_IRCR_HIGH	0x00000001
43 #define TXx9_IRCR_DOWN	0x00000002
44 #define TXx9_IRCR_UP	0x00000003
45 #define TXx9_IRCR_EDGE(cr)	((cr) & 0x00000002)
48 #define TXx9_IRSCR_EIClrE	0x00000100
49 #define TXx9_IRSCR_EIClr_MASK	0x0000000f
52 #define TXx9_IRCSR_IF	0x00010000
53 #define TXx9_IRCSR_ILV_MASK	0x00000700
54 #define TXx9_IRCSR_IVL_MASK	0x0000001f
56 #define irc_dlevel	0
72 	__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))  in txx9_irq_unmask()
83 	__raw_writel((__raw_readl(ilrp) & ~(0xff << ofs))  in txx9_irq_mask()
108 		return 0;  in txx9_irq_set_type()
120 	cr &= ~(0x3 << ofs);  in txx9_irq_set_type()
121 	cr |= (mode & 0x3) << ofs;  in txx9_irq_set_type()
124 	return 0;  in txx9_irq_set_type()
141 	for (i = 0; i < TXx9_MAX_IR; i++) {  in txx9_irq_init()
149 	__raw_writel(0, &txx9_ircptr->imr);  in txx9_irq_init()
150 	for (i = 0; i < 8; i++)  in txx9_irq_init()
151 		__raw_writel(0, &txx9_ircptr->ilr[i]);  in txx9_irq_init()
153 	for (i = 0; i < 2; i++)  in txx9_irq_init()
154 		__raw_writel(0, &txx9_ircptr->cr[i]);  in txx9_irq_init()
165 		return 0;  in txx9_irq_set_pri()