Lines Matching +full:0 +full:x00000700

29 #define SI_CORE_SIZE		0x1000
38 #define SI_PCI_DMA_SZ		0x40000000
41 #define SI_PCIE_DMA_H32		0x80000000
44 #define	SI_CC_IDX		0
52 #define SI_CLK_CTL_ST		0x1e0	/* clock control and status */
55 #define	CCS_FORCEALP		0x00000001	/* force ALP request */
56 #define	CCS_FORCEHT		0x00000002	/* force HT request */
57 #define	CCS_FORCEILP		0x00000004	/* force ILP request */
58 #define	CCS_ALPAREQ		0x00000008	/* ALP Avail Request */
59 #define	CCS_HTAREQ		0x00000010	/* HT Avail Request */
60 #define	CCS_FORCEHWREQOFF	0x00000020	/* Force HW Clock Request Off */
61 #define CCS_ERSRC_REQ_MASK	0x00000700	/* external resource requests */
63 #define	CCS_ALPAVAIL		0x00010000	/* ALP is available */
64 #define	CCS_HTAVAIL		0x00020000	/* HT is available */
65 #define CCS_BP_ON_APL		0x00040000	/* RO: running on ALP clock */
66 #define CCS_BP_ON_HT		0x00080000	/* RO: running on HT clock */
67 #define CCS_ERSRC_STS_MASK	0x07000000	/* external resource status */
71 #define	CCS0_HTAVAIL		0x00010000
73 #define	CCS0_ALPAVAIL		0x00020000
80 #define FLASH_MIN		0x00020000	/* Minimum flash size */
82 #define	CC_SROM_OTP		0x800	/* SROM/OTP address space */
88 #define	CLKD_OTP		0x000f0000
99 #define	ILP_DIV_5MHZ		0	/* ILP = 5 MHz */
103 #define	XTAL			0x1	/* primary crystal oscillator (2050) */
104 #define	PLL			0x2	/* main chip pll */
107 #define GPIO_DRV_PRIORITY	0	/* Driver */
114 #define GPIO_PULLUP		0
118 #define GPIO_REGEVT		0	/* GPIO register event */