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Searched refs:clk_base (Results 1 – 25 of 25) sorted by relevance

/linux-6.12.1/drivers/clk/nuvoton/
Dclk-ma35d1.c463 void __iomem *clk_base; in ma35d1_clocks_probe() local
478 clk_base = devm_platform_ioremap_resource(pdev, 0); in ma35d1_clocks_probe()
479 if (IS_ERR(clk_base)) in ma35d1_clocks_probe()
480 return PTR_ERR(clk_base); in ma35d1_clocks_probe()
490 clk_base + REG_CLK_PWRCTL, 0); in ma35d1_clocks_probe()
493 clk_base + REG_CLK_PWRCTL, 1); in ma35d1_clocks_probe()
496 clk_base + REG_CLK_PWRCTL, 2); in ma35d1_clocks_probe()
499 clk_base + REG_CLK_PWRCTL, 3); in ma35d1_clocks_probe()
502 hws[HXT], clk_base + REG_CLK_PLL0CTL0); in ma35d1_clocks_probe()
505 hws[HXT], clk_base + REG_CLK_PLL2CTL0); in ma35d1_clocks_probe()
[all …]
/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra210.c298 static void __iomem *clk_base; variable
504 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_is_enabled()
520 value = readl_relaxed(clk_base + PLLE_MISC0); in tegra210_plle_hw_sequence_start()
525 writel_relaxed(value, clk_base + PLLE_MISC0); in tegra210_plle_hw_sequence_start()
527 value = readl_relaxed(clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
530 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
532 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
535 writel_relaxed(value, clk_base + PLLE_AUX); in tegra210_plle_hw_sequence_start()
537 fence_udelay(1, clk_base); in tegra210_plle_hw_sequence_start()
547 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0); in tegra210_xusb_pll_hw_control_enable()
[all …]
Dclk-tegra-super-gen4.c95 static void __init tegra_sclk_init(void __iomem *clk_base, in tegra_sclk_init() argument
109 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
119 clk_base + SCLK_DIVIDER, 0, 8, in tegra_sclk_init()
132 clk_base + SCLK_BURST_POLICY, in tegra_sclk_init()
142 clk_base + SYSTEM_CLK_RATE, 4, 2, 0, in tegra_sclk_init()
146 clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
157 clk_base + SYSTEM_CLK_RATE, 0, 2, 0, in tegra_sclk_init()
160 CLK_IS_CRITICAL, clk_base + SYSTEM_CLK_RATE, in tegra_sclk_init()
165 static void __init tegra_super_clk_init(void __iomem *clk_base, in tegra_super_clk_init() argument
182 clk_base + CCLKG_BURST_POLICY, in tegra_super_clk_init()
[all …]
Dclk-tegra20.c132 static void __iomem *clk_base; variable
574 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL); in tegra20_clk_measure_input_freq()
608 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div()
630 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
636 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
639 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra20_pll_init()
644 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL, in tegra20_pll_init()
650 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra20_pll_init()
653 clk_base + PLLM_OUT, 1, 0, in tegra20_pll_init()
658 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0, in tegra20_pll_init()
[all …]
Dclk-tegra30.c150 static void __iomem *clk_base; variable
819 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
822 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT, in tegra30_pll_init()
828 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra30_pll_init()
831 clk_base + PLLM_OUT, 1, 0, in tegra30_pll_init()
836 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
846 clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0, in tegra30_pll_init()
851 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
861 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, in tegra30_pll_init()
874 clk_base + PLLE_AUX, 2, 1, 0, NULL); in tegra30_pll_init()
[all …]
Dclk-tegra114.c130 static void __iomem *clk_base; variable
890 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) in tegra114_fixed_clk_init() argument
899 static void __init tegra114_pll_init(void __iomem *clk_base, in tegra114_pll_init() argument
905 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, in tegra114_pll_init()
911 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
914 clk_base + PLLC_OUT, 1, 0, in tegra114_pll_init()
919 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
924 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
929 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, in tegra114_pll_init()
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
[all …]
Dclk.h379 void __iomem *clk_base; member
405 void __iomem *clk_base, void __iomem *pmc,
410 void __iomem *clk_base, void __iomem *pmc,
415 void __iomem *clk_base, void __iomem *pmc,
421 void __iomem *clk_base, void __iomem *pmc,
427 void __iomem *clk_base, void __iomem *pmc,
433 void __iomem *clk_base, void __iomem *pmc,
439 const char *parent_name, void __iomem *clk_base,
446 void __iomem *clk_base, unsigned long flags,
452 void __iomem *clk_base, unsigned long flags,
[all …]
Dclk-periph-gate.c20 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
22 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
24 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
27 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
29 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
59 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
60 writel_relaxed(BIT(22), gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
62 writel_relaxed(0, gate->clk_base + LVL2_CLK_GATE_OVRE); in clk_periph_enable_locked()
137 const char *parent_name, u8 gate_flags, void __iomem *clk_base, in tegra_clk_register_periph_gate() argument
162 gate->clk_base = clk_base; in tegra_clk_register_periph_gate()
Dclk-tegra-audio.c128 static void __init tegra_audio_sync_clk_init(void __iomem *clk_base, in tegra_audio_sync_clk_init() argument
148 clk_base + data->offset, 0, 3, 0, in tegra_audio_sync_clk_init()
157 0, clk_base + data->offset, 4, in tegra_audio_sync_clk_init()
163 void __init tegra_audio_clk_init(void __iomem *clk_base, in tegra_audio_clk_init() argument
184 clk_base, pmc_base, 0, info->pll_params, in tegra_audio_clk_init()
194 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra_audio_clk_init()
197 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra_audio_clk_init()
215 tegra_audio_sync_clk_init(clk_base, tegra_clks, audio_clks, in tegra_audio_clk_init()
221 writel_relaxed(1, clk_base + dmic_clks[i].offset); in tegra_audio_clk_init()
223 tegra_audio_sync_clk_init(clk_base, tegra_clks, dmic_clks, in tegra_audio_clk_init()
[all …]
Dclk-tegra124.c119 static void __iomem *clk_base; variable
1024 static __init void tegra124_periph_clk_init(void __iomem *clk_base, in tegra124_periph_clk_init() argument
1035 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, in tegra124_periph_clk_init()
1040 clk_base + PLLD_MISC, 30, 0, &pll_d_lock); in tegra124_periph_clk_init()
1044 clk_base, 0, 48, in tegra124_periph_clk_init()
1049 clk_base, 0, 82, in tegra124_periph_clk_init()
1053 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC, in tegra124_periph_clk_init()
1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1079 clk = tegra_clk_register_periph_data(clk_base, init); in tegra124_periph_clk_init()
[all …]
Dclk-tegra-fixed.c25 int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks, in tegra_osc_clk_init() argument
35 val = readl_relaxed(clk_base + OSC_CTRL); in tegra_osc_clk_init()
110 void tegra_clk_osc_resume(void __iomem *clk_base) in tegra_clk_osc_resume() argument
114 val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK; in tegra_clk_osc_resume()
116 writel_relaxed(val, clk_base + OSC_CTRL); in tegra_clk_osc_resume()
117 fence_udelay(2, clk_base); in tegra_clk_osc_resume()
Dclk-periph.c171 void __iomem *clk_base, u32 offset, in _tegra_clk_register_periph() argument
199 periph->mux.reg = clk_base + offset; in _tegra_clk_register_periph()
200 periph->divider.reg = div ? (clk_base + offset) : NULL; in _tegra_clk_register_periph()
201 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
218 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph() argument
222 periph, clk_base, offset, flags); in tegra_clk_register_periph()
227 struct tegra_clk_periph *periph, void __iomem *clk_base, in tegra_clk_register_periph_nodiv() argument
232 periph, clk_base, offset, CLK_SET_RATE_PARENT); in tegra_clk_register_periph_nodiv()
235 struct clk *tegra_clk_register_periph_data(void __iomem *clk_base, in tegra_clk_register_periph_data() argument
240 clk_base, init->offset, init->flags); in tegra_clk_register_periph_data()
Dclk.c99 static void __iomem *clk_base; variable
115 clk_base + periph_regs[id / 32].rst_set_reg); in tegra_clk_rst_assert()
129 clk_base + periph_regs[id / 32].rst_clr_reg); in tegra_clk_rst_deassert()
168 val = readl_relaxed(clk_base + CLK_OUT_ENB_Y); in tegra_clk_set_pllp_out_cpu()
174 writel_relaxed(val, clk_base + CLK_OUT_ENB_Y); in tegra_clk_set_pllp_out_cpu()
184 readl_relaxed(clk_base + periph_regs[i].enb_reg); in tegra_clk_periph_suspend()
188 readl_relaxed(clk_base + periph_regs[i].rst_reg); in tegra_clk_periph_suspend()
198 clk_base + periph_regs[i].enb_reg); in tegra_clk_periph_resume()
204 fence_udelay(5, clk_base); in tegra_clk_periph_resume()
208 clk_base + periph_regs[i].rst_reg); in tegra_clk_periph_resume()
[all …]
Dclk-pll.c230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
1002 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1005 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1162 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1172 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1174 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1184 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1268 void __iomem *clk_base, in _setup_dynamic_ramp() argument
[all …]
Dclk-tegra-periph.c860 static void __init periph_clk_init(void __iomem *clk_base, in periph_clk_init() argument
882 clk = tegra_clk_register_periph_data(clk_base, data); in periph_clk_init()
887 static void __init gate_clk_init(void __iomem *clk_base, in gate_clk_init() argument
905 clk_base, data->flags, in gate_clk_init()
912 static void __init div_clk_init(void __iomem *clk_base, in div_clk_init() argument
929 data->p.parent_name, clk_base + data->offset, in div_clk_init()
939 static void __init init_pllp(void __iomem *clk_base, void __iomem *pmc_base, in init_pllp() argument
950 clk = tegra_clk_register_pll("pll_p", "pll_ref", clk_base, in init_pllp()
966 clk_base + data->offset, 0, data->div_flags, in init_pllp()
969 data->div_name, clk_base + data->offset, in init_pllp()
[all …]
Dclk-sdmmc-mux.c235 void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, in tegra_clk_register_sdmmc_mux_div() argument
259 sdmmc_mux->reg = clk_base + offset; in tegra_clk_register_sdmmc_mux_div()
261 sdmmc_mux->gate.clk_base = clk_base; in tegra_clk_register_sdmmc_mux_div()
/linux-6.12.1/drivers/clk/
Dclk-npcm7xx.c407 void __iomem *clk_base; in npcm7xx_clk_init() local
420 clk_base = ioremap(res.start, resource_size(&res)); in npcm7xx_clk_init()
421 if (!clk_base) in npcm7xx_clk_init()
438 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, in npcm7xx_clk_init()
471 mux_data->flags, clk_base + NPCM7XX_CLKSEL, in npcm7xx_clk_init()
491 clk_base + div_data->reg, in npcm7xx_clk_init()
515 iounmap(clk_base); in npcm7xx_clk_init()
Dclk-sp7021.c601 void __iomem *clk_base, *pll_base, *sys_base; in sp7021_clk_probe() local
606 clk_base = devm_platform_ioremap_resource(pdev, 0); in sp7021_clk_probe()
607 if (IS_ERR(clk_base)) in sp7021_clk_probe()
608 return PTR_ERR(clk_base); in sp7021_clk_probe()
618 writel((sp_clken[i] << 16) | sp_clken[i], clk_base + i * 4); in sp7021_clk_probe()
684 clk_base + (j >> 4) * 4, in sp7021_clk_probe()
/linux-6.12.1/drivers/clk/ralink/
Dclk-mtmips.c99 struct mtmips_clk *clk_base; member
725 sclk = &priv->data->clk_base[i]; in mtmips_register_clocks()
740 sclk = &priv->data->clk_base[i]; in mtmips_register_clocks()
747 .clk_base = rt2880_clks_base,
758 .clk_base = rt305x_clks_base,
769 .clk_base = rt3352_clks_base,
780 .clk_base = rt3883_clks_base,
791 .clk_base = rt5350_clks_base,
802 .clk_base = mt7620_clks_base,
813 .clk_base = mt76x8_clks_base,
[all …]
/linux-6.12.1/drivers/pinctrl/samsung/
Dpinctrl-exynos-arm.c58 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv; in s5pv210_retention_disable() local
61 tmp = __raw_readl(clk_base + S5P_OTHERS); in s5pv210_retention_disable()
64 __raw_writel(tmp, clk_base + S5P_OTHERS); in s5pv210_retention_disable()
73 void __iomem *clk_base; in s5pv210_retention_init() local
86 clk_base = of_iomap(np, 0); in s5pv210_retention_init()
88 if (!clk_base) { in s5pv210_retention_init()
93 ctrl->priv = (void __force *)clk_base; in s5pv210_retention_init()
Dpinctrl-exynos.c482 void __iomem *clk_base; in s5pv210_pinctrl_set_eint_wakeup_mask() local
491 clk_base = (void __iomem *) drvdata->retention_ctrl->priv; in s5pv210_pinctrl_set_eint_wakeup_mask()
494 clk_base + irq_chip->eint_wake_mask_reg); in s5pv210_pinctrl_set_eint_wakeup_mask()
/linux-6.12.1/drivers/cpufreq/
Ds5pv210-cpufreq.c24 static void __iomem *clk_base; variable
27 #define S5P_CLKREG(x) (clk_base + (x))
624 clk_base = of_iomap(np, 0); in s5pv210_cpufreq_probe()
626 if (!clk_base) { in s5pv210_cpufreq_probe()
670 iounmap(clk_base); in s5pv210_cpufreq_probe()
Darmada-37xx-cpufreq.c133 struct regmap *clk_base, u8 *divider) in armada37xx_cpufreq_dvfs_setup() argument
139 regmap_read(clk_base, ARMADA_37XX_CLK_TBG_SEL, &cpu_tbg_sel); in armada37xx_cpufreq_dvfs_setup()
/linux-6.12.1/drivers/clk/nxp/
Dclk-lpc18xx-cgu.c633 static struct clk *clk_base[BASE_CLK_MAX]; variable
635 .clks = clk_base,
644 clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i], in lpc18xx_cgu_register_base_clks()
646 if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT) in lpc18xx_cgu_register_base_clks()
/linux-6.12.1/drivers/mmc/host/
Dsdhci-of-at91.c173 unsigned int clk_base, clk_mul; in sdhci_at91_set_clks_presets() local
187 clk_base = clk_base_rate / 1000000; in sdhci_at91_set_clks_presets()
191 caps0 |= FIELD_PREP(SDHCI_CLOCK_V3_BASE_MASK, clk_base); in sdhci_at91_set_clks_presets()