132 static void __iomem *clk_base;  variable
574 	u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);  in tegra20_clk_measure_input_freq()
608 	u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &  in tegra20_get_pll_ref_div()
630 	clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,  in tegra20_pll_init()
636 				clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra20_pll_init()
639 				clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,  in tegra20_pll_init()
644 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,  in tegra20_pll_init()
650 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra20_pll_init()
653 				clk_base + PLLM_OUT, 1, 0,  in tegra20_pll_init()
658 	clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,  in tegra20_pll_init()
663 	clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,  in tegra20_pll_init()
668 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,  in tegra20_pll_init()
678 	clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,  in tegra20_pll_init()
684 				clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra20_pll_init()
687 				clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra20_pll_init()
692 	clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,  in tegra20_pll_init()
711 			      clk_base + CCLK_BURST_POLICY, TEGRA20_SUPER_CLK,  in tegra20_super_clk_init()
732 				clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);  in tegra20_audio_clk_init()
734 				clk_base + AUDIO_SYNC_CLK, 4,  in tegra20_audio_clk_init()
742 				    TEGRA_PERIPH_NO_RESET, clk_base,  in tegra20_audio_clk_init()
792 				    clk_base, 0, 3, periph_clk_enb_refcnt);  in tegra20_periph_clk_init()
796 	clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);  in tegra20_periph_clk_init()
800 	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,  in tegra20_periph_clk_init()
805 	clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,  in tegra20_periph_clk_init()
811 	clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,  in tegra20_periph_clk_init()
817 			     0, clk_base + MISC_CLK_ENB, 22, 2,  in tegra20_periph_clk_init()
823 			     0, clk_base + MISC_CLK_ENB, 20, 2,  in tegra20_periph_clk_init()
829 				    clk_base, 0, 94, periph_clk_enb_refcnt);  in tegra20_periph_clk_init()
834 				    clk_base, 0, 93, periph_clk_enb_refcnt);  in tegra20_periph_clk_init()
839 		clk = tegra_clk_register_periph_data(clk_base, data);  in tegra20_periph_clk_init()
848 					clk_base, data->offset);  in tegra20_periph_clk_init()
852 	tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);  in tegra20_periph_clk_init()
881 		reg = readl(clk_base +  in tegra20_wait_cpu_in_reset()
892 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);  in tegra20_put_cpu_in_reset()
899 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);  in tegra20_cpu_out_of_reset()
907 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_enable_cpu_clock()
909 	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_enable_cpu_clock()
911 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_enable_cpu_clock()
918 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_disable_cpu_clock()
920 	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra20_disable_cpu_clock()
928 	cpu_rst_status = readl(clk_base +  in tegra20_cpu_rail_off_ready()
938 				readl(clk_base + CLK_SOURCE_CSITE);  in tegra20_cpu_clock_suspend()
939 	writel(3<<30, clk_base + CLK_SOURCE_CSITE);  in tegra20_cpu_clock_suspend()
942 				readl(clk_base + CCLK_BURST_POLICY);  in tegra20_cpu_clock_suspend()
944 				readl(clk_base + PLLX_BASE);  in tegra20_cpu_clock_suspend()
946 				readl(clk_base + PLLX_MISC);  in tegra20_cpu_clock_suspend()
948 				readl(clk_base + SUPER_CCLK_DIVIDER);  in tegra20_cpu_clock_suspend()
957 	reg = readl(clk_base + CCLK_BURST_POLICY);  in tegra20_cpu_clock_resume()
968 		misc = readl_relaxed(clk_base + PLLX_MISC);  in tegra20_cpu_clock_resume()
969 		base = readl_relaxed(clk_base + PLLX_BASE);  in tegra20_cpu_clock_resume()
975 						clk_base + PLLX_MISC);  in tegra20_cpu_clock_resume()
977 						clk_base + PLLX_BASE);  in tegra20_cpu_clock_resume()
990 					clk_base + SUPER_CCLK_DIVIDER);  in tegra20_cpu_clock_resume()
992 					clk_base + CCLK_BURST_POLICY);  in tegra20_cpu_clock_resume()
995 					clk_base + CLK_SOURCE_CSITE);  in tegra20_cpu_clock_resume()
1121 	clk_base = of_iomap(np, 0);  in tegra20_clock_init()
1122 	if (!clk_base) {  in tegra20_clock_init()
1140 	clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,  in tegra20_clock_init()
1149 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);  in tegra20_clock_init()
1177 			      clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);  in tegra20_car_probe()