Lines Matching refs:clk_base
130 static void __iomem *clk_base; variable
890 static void __init tegra114_fixed_clk_init(void __iomem *clk_base) in tegra114_fixed_clk_init() argument
899 static void __init tegra114_pll_init(void __iomem *clk_base, in tegra114_pll_init() argument
905 clk = tegra_clk_register_pllxc("pll_c", "pll_ref", clk_base, in tegra114_pll_init()
911 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
914 clk_base + PLLC_OUT, 1, 0, in tegra114_pll_init()
919 clk = tegra_clk_register_pllc("pll_c2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
924 clk = tegra_clk_register_pllc("pll_c3", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
929 clk = tegra_clk_register_pllm("pll_m", "pll_ref", clk_base, pmc, in tegra114_pll_init()
935 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP, in tegra114_pll_init()
938 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED | in tegra114_pll_init()
947 clk = tegra_clk_register_pllu_tegra114("pll_u", "pll_ref", clk_base, 0, in tegra114_pll_init()
953 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra114_pll_init()
973 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
983 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc, 0, in tegra114_pll_init()
993 clk = tegra_clk_register_pllre("pll_re_vco", "pll_ref", clk_base, pmc, in tegra114_pll_init()
998 clk_base + PLLRE_BASE, 16, 4, 0, in tegra114_pll_init()
1004 clk_base, 0, &pll_e_params, NULL); in tegra114_pll_init()
1014 static __init void tegra114_periph_clk_init(void __iomem *clk_base, in tegra114_periph_clk_init() argument
1030 clk_base + PLLD_BASE, 25, 1, 0, &pll_d_lock); in tegra114_periph_clk_init()
1037 clk_base + PLLD2_BASE, 25, 1, 0, &pll_d2_lock); in tegra114_periph_clk_init()
1040 clk = tegra_clk_register_periph_gate("dsia", "dsia_mux", 0, clk_base, in tegra114_periph_clk_init()
1044 clk = tegra_clk_register_periph_gate("dsib", "dsib_mux", 0, clk_base, in tegra114_periph_clk_init()
1052 clk_base + CLK_SOURCE_EMC, in tegra114_periph_clk_init()
1055 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, in tegra114_periph_clk_init()
1059 clk = tegra_clk_register_periph_gate("mipi-cal", "clk_m", 0, clk_base, in tegra114_periph_clk_init()
1066 clk = tegra_clk_register_periph_data(clk_base, data); in tegra114_periph_clk_init()
1070 tegra_periph_clk_init(clk_base, pmc_base, tegra114_clks, in tegra114_periph_clk_init()
1080 reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS); in tegra114_wait_cpu_in_reset()
1095 readl(clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_suspend()
1096 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_suspend()
1099 readl(clk_base + CCLKG_BURST_POLICY); in tegra114_cpu_clock_suspend()
1101 readl(clk_base + CCLKG_BURST_POLICY + 4); in tegra114_cpu_clock_suspend()
1107 clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_resume()
1110 clk_base + CCLKG_BURST_POLICY); in tegra114_cpu_clock_resume()
1112 clk_base + CCLKG_BURST_POLICY + 4); in tegra114_cpu_clock_resume()
1188 readl_relaxed(clk_base + CPU_FINETRIM_SELECT); in tegra114_car_barrier()
1206 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); in tegra114_clock_tune_cpu_trimmers_high()
1233 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); in tegra114_clock_tune_cpu_trimmers_low()
1255 writel_relaxed(r, clk_base + CPU_FINETRIM_R); in tegra114_clock_tune_cpu_trimmers_init()
1264 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); in tegra114_clock_tune_cpu_trimmers_init()
1279 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra114_clock_assert_dfll_dvco_reset()
1281 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra114_clock_assert_dfll_dvco_reset()
1296 v = readl_relaxed(clk_base + RST_DFLL_DVCO); in tegra114_clock_deassert_dfll_dvco_reset()
1298 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra114_clock_deassert_dfll_dvco_reset()
1307 clk_base = of_iomap(np, 0); in tegra114_clock_init()
1308 if (!clk_base) { in tegra114_clock_init()
1328 clks = tegra_clk_init(clk_base, TEGRA114_CLK_CLK_MAX, in tegra114_clock_init()
1333 if (tegra_osc_clk_init(clk_base, tegra114_clks, tegra114_input_freq, in tegra114_clock_init()
1338 tegra114_fixed_clk_init(clk_base); in tegra114_clock_init()
1339 tegra114_pll_init(clk_base, pmc_base); in tegra114_clock_init()
1340 tegra114_periph_clk_init(clk_base, pmc_base); in tegra114_clock_init()
1341 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks, in tegra114_clock_init()
1344 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks, in tegra114_clock_init()