Lines Matching refs:clk_base
463 void __iomem *clk_base; in ma35d1_clocks_probe() local
478 clk_base = devm_platform_ioremap_resource(pdev, 0); in ma35d1_clocks_probe()
479 if (IS_ERR(clk_base)) in ma35d1_clocks_probe()
480 return PTR_ERR(clk_base); in ma35d1_clocks_probe()
490 clk_base + REG_CLK_PWRCTL, 0); in ma35d1_clocks_probe()
493 clk_base + REG_CLK_PWRCTL, 1); in ma35d1_clocks_probe()
496 clk_base + REG_CLK_PWRCTL, 2); in ma35d1_clocks_probe()
499 clk_base + REG_CLK_PWRCTL, 3); in ma35d1_clocks_probe()
502 hws[HXT], clk_base + REG_CLK_PLL0CTL0); in ma35d1_clocks_probe()
505 hws[HXT], clk_base + REG_CLK_PLL2CTL0); in ma35d1_clocks_probe()
507 hws[HXT], clk_base + REG_CLK_PLL3CTL0); in ma35d1_clocks_probe()
509 hws[HXT], clk_base + REG_CLK_PLL4CTL0); in ma35d1_clocks_probe()
511 hws[HXT], clk_base + REG_CLK_PLL5CTL0); in ma35d1_clocks_probe()
518 clk_base + REG_CLK_CLKSEL0, 0, 2, in ma35d1_clocks_probe()
524 hws[AXICLK_MUX] = ma35d1_clk_mux(dev, "axiclk_mux", clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()
527 hws[SYSCLK0_MUX] = ma35d1_clk_mux(dev, "sysclk0_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
530 hws[SYSCLK1_MUX] = ma35d1_clk_mux(dev, "sysclk1_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
552 clk_base + REG_CLK_SYSCLK0, 4); in ma35d1_clocks_probe()
554 clk_base + REG_CLK_SYSCLK0, 5); in ma35d1_clocks_probe()
556 hws[CAN0_MUX] = ma35d1_clk_mux(dev, "can0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
559 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()
562 clk_base + REG_CLK_SYSCLK0, 8); in ma35d1_clocks_probe()
563 hws[CAN1_MUX] = ma35d1_clk_mux(dev, "can1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
566 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()
569 clk_base + REG_CLK_SYSCLK0, 9); in ma35d1_clocks_probe()
570 hws[CAN2_MUX] = ma35d1_clk_mux(dev, "can2_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
573 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()
576 clk_base + REG_CLK_SYSCLK0, 10); in ma35d1_clocks_probe()
577 hws[CAN3_MUX] = ma35d1_clk_mux(dev, "can3_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
580 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()
583 clk_base + REG_CLK_SYSCLK0, 11); in ma35d1_clocks_probe()
585 hws[SDH0_MUX] = ma35d1_clk_mux(dev, "sdh0_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
588 clk_base + REG_CLK_SYSCLK0, 16); in ma35d1_clocks_probe()
589 hws[SDH1_MUX] = ma35d1_clk_mux(dev, "sdh1_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
592 clk_base + REG_CLK_SYSCLK0, 17); in ma35d1_clocks_probe()
595 clk_base + REG_CLK_SYSCLK0, 18); in ma35d1_clocks_probe()
598 clk_base + REG_CLK_SYSCLK0, 19); in ma35d1_clocks_probe()
600 clk_base + REG_CLK_SYSCLK0, 20); in ma35d1_clocks_probe()
602 clk_base + REG_CLK_SYSCLK0, 21); in ma35d1_clocks_probe()
604 clk_base + REG_CLK_SYSCLK0, 22); in ma35d1_clocks_probe()
606 hws[GFX_MUX] = ma35d1_clk_mux(dev, "gfx_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
609 clk_base + REG_CLK_SYSCLK0, 24); in ma35d1_clocks_probe()
611 clk_base + REG_CLK_SYSCLK0, 25); in ma35d1_clocks_probe()
612 hws[DCU_MUX] = ma35d1_clk_mux(dev, "dcu_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
615 clk_base + REG_CLK_SYSCLK0, 26); in ma35d1_clocks_probe()
617 clk_base + REG_CLK_CLKDIV0, in ma35d1_clocks_probe()
621 clk_base + REG_CLK_SYSCLK0, 27); in ma35d1_clocks_probe()
623 clk_base + REG_CLK_SYSCLK0, 28); in ma35d1_clocks_probe()
625 hws[CCAP0_MUX] = ma35d1_clk_mux(dev, "ccap0_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
628 clk_base + REG_CLK_CLKDIV1, 8, 4); in ma35d1_clocks_probe()
630 clk_base + REG_CLK_SYSCLK0, 29); in ma35d1_clocks_probe()
631 hws[CCAP1_MUX] = ma35d1_clk_mux(dev, "ccap1_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
634 clk_base + REG_CLK_CLKDIV1, in ma35d1_clocks_probe()
637 clk_base + REG_CLK_SYSCLK0, 30); in ma35d1_clocks_probe()
640 clk_base + REG_CLK_SYSCLK1, 0); in ma35d1_clocks_probe()
642 clk_base + REG_CLK_SYSCLK1, 1); in ma35d1_clocks_probe()
644 clk_base + REG_CLK_SYSCLK1, 2); in ma35d1_clocks_probe()
646 clk_base + REG_CLK_SYSCLK1, 3); in ma35d1_clocks_probe()
649 clk_base + REG_CLK_SYSCLK1, 4); in ma35d1_clocks_probe()
651 clk_base + REG_CLK_SYSCLK1, 5); in ma35d1_clocks_probe()
654 clk_base + REG_CLK_SYSCLK1, 6); in ma35d1_clocks_probe()
657 clk_base + REG_CLK_SYSCLK1, 7); in ma35d1_clocks_probe()
660 clk_base + REG_CLK_SYSCLK1, 8); in ma35d1_clocks_probe()
662 clk_base + REG_CLK_SYSCLK1, 9); in ma35d1_clocks_probe()
665 clk_base + REG_CLK_SYSCLK1, 10); in ma35d1_clocks_probe()
668 clk_base + REG_CLK_SYSCLK1, 11); in ma35d1_clocks_probe()
670 hws[DBG_MUX] = ma35d1_clk_mux(dev, "dbg_mux", clk_base + REG_CLK_CLKSEL0, in ma35d1_clocks_probe()
673 clk_base + REG_CLK_SYSCLK1, 12); in ma35d1_clocks_probe()
675 hws[CKO_MUX] = ma35d1_clk_mux(dev, "cko_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
678 clk_base + REG_CLK_CLKOCTL, 0, 4); in ma35d1_clocks_probe()
680 clk_base + REG_CLK_SYSCLK1, 13); in ma35d1_clocks_probe()
683 clk_base + REG_CLK_SYSCLK1, 14); in ma35d1_clocks_probe()
686 clk_base + REG_CLK_SYSCLK1, 16); in ma35d1_clocks_probe()
688 clk_base + REG_CLK_SYSCLK1, 17); in ma35d1_clocks_probe()
690 clk_base + REG_CLK_SYSCLK1, 18); in ma35d1_clocks_probe()
692 clk_base + REG_CLK_SYSCLK1, 19); in ma35d1_clocks_probe()
694 clk_base + REG_CLK_SYSCLK1, 20); in ma35d1_clocks_probe()
696 clk_base + REG_CLK_SYSCLK1, 21); in ma35d1_clocks_probe()
698 clk_base + REG_CLK_SYSCLK1, 22); in ma35d1_clocks_probe()
700 clk_base + REG_CLK_SYSCLK1, 23); in ma35d1_clocks_probe()
702 clk_base + REG_CLK_SYSCLK1, 24); in ma35d1_clocks_probe()
704 clk_base + REG_CLK_SYSCLK1, 25); in ma35d1_clocks_probe()
706 clk_base + REG_CLK_SYSCLK1, 26); in ma35d1_clocks_probe()
708 clk_base + REG_CLK_SYSCLK1, 27); in ma35d1_clocks_probe()
710 clk_base + REG_CLK_SYSCLK1, 28); in ma35d1_clocks_probe()
712 clk_base + REG_CLK_SYSCLK1, 29); in ma35d1_clocks_probe()
714 hws[TMR0_MUX] = ma35d1_clk_mux(dev, "tmr0_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
718 clk_base + REG_CLK_APBCLK0, 0); in ma35d1_clocks_probe()
719 hws[TMR1_MUX] = ma35d1_clk_mux(dev, "tmr1_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
723 clk_base + REG_CLK_APBCLK0, 1); in ma35d1_clocks_probe()
724 hws[TMR2_MUX] = ma35d1_clk_mux(dev, "tmr2_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
728 clk_base + REG_CLK_APBCLK0, 2); in ma35d1_clocks_probe()
729 hws[TMR3_MUX] = ma35d1_clk_mux(dev, "tmr3_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
733 clk_base + REG_CLK_APBCLK0, 3); in ma35d1_clocks_probe()
734 hws[TMR4_MUX] = ma35d1_clk_mux(dev, "tmr4_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
738 clk_base + REG_CLK_APBCLK0, 4); in ma35d1_clocks_probe()
739 hws[TMR5_MUX] = ma35d1_clk_mux(dev, "tmr5_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
743 clk_base + REG_CLK_APBCLK0, 5); in ma35d1_clocks_probe()
744 hws[TMR6_MUX] = ma35d1_clk_mux(dev, "tmr6_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
748 clk_base + REG_CLK_APBCLK0, 6); in ma35d1_clocks_probe()
749 hws[TMR7_MUX] = ma35d1_clk_mux(dev, "tmr7_mux", clk_base + REG_CLK_CLKSEL1, in ma35d1_clocks_probe()
753 clk_base + REG_CLK_APBCLK0, 7); in ma35d1_clocks_probe()
754 hws[TMR8_MUX] = ma35d1_clk_mux(dev, "tmr8_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
758 clk_base + REG_CLK_APBCLK0, 8); in ma35d1_clocks_probe()
759 hws[TMR9_MUX] = ma35d1_clk_mux(dev, "tmr9_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
763 clk_base + REG_CLK_APBCLK0, 9); in ma35d1_clocks_probe()
764 hws[TMR10_MUX] = ma35d1_clk_mux(dev, "tmr10_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
768 clk_base + REG_CLK_APBCLK0, 10); in ma35d1_clocks_probe()
769 hws[TMR11_MUX] = ma35d1_clk_mux(dev, "tmr11_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
773 clk_base + REG_CLK_APBCLK0, 11); in ma35d1_clocks_probe()
775 hws[UART0_MUX] = ma35d1_clk_mux(dev, "uart0_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
778 clk_base + REG_CLK_CLKDIV1, in ma35d1_clocks_probe()
781 clk_base + REG_CLK_APBCLK0, 12); in ma35d1_clocks_probe()
782 hws[UART1_MUX] = ma35d1_clk_mux(dev, "uart1_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
785 clk_base + REG_CLK_CLKDIV1, in ma35d1_clocks_probe()
788 clk_base + REG_CLK_APBCLK0, 13); in ma35d1_clocks_probe()
789 hws[UART2_MUX] = ma35d1_clk_mux(dev, "uart2_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
792 clk_base + REG_CLK_CLKDIV1, in ma35d1_clocks_probe()
795 clk_base + REG_CLK_APBCLK0, 14); in ma35d1_clocks_probe()
796 hws[UART3_MUX] = ma35d1_clk_mux(dev, "uart3_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
799 clk_base + REG_CLK_CLKDIV1, in ma35d1_clocks_probe()
802 clk_base + REG_CLK_APBCLK0, 15); in ma35d1_clocks_probe()
803 hws[UART4_MUX] = ma35d1_clk_mux(dev, "uart4_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
806 clk_base + REG_CLK_CLKDIV2, in ma35d1_clocks_probe()
809 clk_base + REG_CLK_APBCLK0, 16); in ma35d1_clocks_probe()
810 hws[UART5_MUX] = ma35d1_clk_mux(dev, "uart5_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
813 clk_base + REG_CLK_CLKDIV2, in ma35d1_clocks_probe()
816 clk_base + REG_CLK_APBCLK0, 17); in ma35d1_clocks_probe()
817 hws[UART6_MUX] = ma35d1_clk_mux(dev, "uart6_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
820 clk_base + REG_CLK_CLKDIV2, in ma35d1_clocks_probe()
823 clk_base + REG_CLK_APBCLK0, 18); in ma35d1_clocks_probe()
824 hws[UART7_MUX] = ma35d1_clk_mux(dev, "uart7_mux", clk_base + REG_CLK_CLKSEL2, in ma35d1_clocks_probe()
827 clk_base + REG_CLK_CLKDIV2, in ma35d1_clocks_probe()
830 clk_base + REG_CLK_APBCLK0, 19); in ma35d1_clocks_probe()
831 hws[UART8_MUX] = ma35d1_clk_mux(dev, "uart8_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
834 clk_base + REG_CLK_CLKDIV2, in ma35d1_clocks_probe()
837 clk_base + REG_CLK_APBCLK0, 20); in ma35d1_clocks_probe()
838 hws[UART9_MUX] = ma35d1_clk_mux(dev, "uart9_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
841 clk_base + REG_CLK_CLKDIV2, in ma35d1_clocks_probe()
844 clk_base + REG_CLK_APBCLK0, 21); in ma35d1_clocks_probe()
845 hws[UART10_MUX] = ma35d1_clk_mux(dev, "uart10_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
848 clk_base + REG_CLK_CLKDIV2, in ma35d1_clocks_probe()
851 clk_base + REG_CLK_APBCLK0, 22); in ma35d1_clocks_probe()
852 hws[UART11_MUX] = ma35d1_clk_mux(dev, "uart11_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
855 clk_base + REG_CLK_CLKDIV2, in ma35d1_clocks_probe()
858 clk_base + REG_CLK_APBCLK0, 23); in ma35d1_clocks_probe()
859 hws[UART12_MUX] = ma35d1_clk_mux(dev, "uart12_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
862 clk_base + REG_CLK_CLKDIV3, in ma35d1_clocks_probe()
865 clk_base + REG_CLK_APBCLK0, 24); in ma35d1_clocks_probe()
866 hws[UART13_MUX] = ma35d1_clk_mux(dev, "uart13_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
869 clk_base + REG_CLK_CLKDIV3, in ma35d1_clocks_probe()
872 clk_base + REG_CLK_APBCLK0, 25); in ma35d1_clocks_probe()
873 hws[UART14_MUX] = ma35d1_clk_mux(dev, "uart14_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
876 clk_base + REG_CLK_CLKDIV3, in ma35d1_clocks_probe()
879 clk_base + REG_CLK_APBCLK0, 26); in ma35d1_clocks_probe()
880 hws[UART15_MUX] = ma35d1_clk_mux(dev, "uart15_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
883 clk_base + REG_CLK_CLKDIV3, in ma35d1_clocks_probe()
886 clk_base + REG_CLK_APBCLK0, 27); in ma35d1_clocks_probe()
887 hws[UART16_MUX] = ma35d1_clk_mux(dev, "uart16_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
890 clk_base + REG_CLK_CLKDIV3, in ma35d1_clocks_probe()
893 clk_base + REG_CLK_APBCLK0, 28); in ma35d1_clocks_probe()
896 clk_base + REG_CLK_APBCLK0, 29); in ma35d1_clocks_probe()
898 clk_base + REG_CLK_APBCLK0, 30); in ma35d1_clocks_probe()
900 hws[KPI_MUX] = ma35d1_clk_mux(dev, "kpi_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
903 clk_base + REG_CLK_CLKDIV4, in ma35d1_clocks_probe()
906 clk_base + REG_CLK_APBCLK0, 31); in ma35d1_clocks_probe()
909 clk_base + REG_CLK_APBCLK1, 0); in ma35d1_clocks_probe()
911 clk_base + REG_CLK_APBCLK1, 1); in ma35d1_clocks_probe()
913 clk_base + REG_CLK_APBCLK1, 2); in ma35d1_clocks_probe()
915 clk_base + REG_CLK_APBCLK1, 3); in ma35d1_clocks_probe()
917 clk_base + REG_CLK_APBCLK1, 4); in ma35d1_clocks_probe()
919 clk_base + REG_CLK_APBCLK1, 5); in ma35d1_clocks_probe()
921 hws[QSPI0_MUX] = ma35d1_clk_mux(dev, "qspi0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
924 clk_base + REG_CLK_APBCLK1, 6); in ma35d1_clocks_probe()
925 hws[QSPI1_MUX] = ma35d1_clk_mux(dev, "qspi1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
928 clk_base + REG_CLK_APBCLK1, 7); in ma35d1_clocks_probe()
930 hws[SMC0_MUX] = ma35d1_clk_mux(dev, "smc0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
933 clk_base + REG_CLK_CLKDIV1, in ma35d1_clocks_probe()
936 clk_base + REG_CLK_APBCLK1, 12); in ma35d1_clocks_probe()
937 hws[SMC1_MUX] = ma35d1_clk_mux(dev, "smc1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
940 clk_base + REG_CLK_CLKDIV1, in ma35d1_clocks_probe()
943 clk_base + REG_CLK_APBCLK1, 13); in ma35d1_clocks_probe()
945 hws[WDT0_MUX] = ma35d1_clk_mux(dev, "wdt0_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
948 clk_base + REG_CLK_APBCLK1, 16); in ma35d1_clocks_probe()
949 hws[WDT1_MUX] = ma35d1_clk_mux(dev, "wdt1_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
952 clk_base + REG_CLK_APBCLK1, 17); in ma35d1_clocks_probe()
953 hws[WDT2_MUX] = ma35d1_clk_mux(dev, "wdt2_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
956 clk_base + REG_CLK_APBCLK1, 18); in ma35d1_clocks_probe()
958 hws[WWDT0_MUX] = ma35d1_clk_mux(dev, "wwdt0_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
960 hws[WWDT1_MUX] = ma35d1_clk_mux(dev, "wwdt1_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
962 hws[WWDT2_MUX] = ma35d1_clk_mux(dev, "wwdt2_mux", clk_base + REG_CLK_CLKSEL3, in ma35d1_clocks_probe()
966 clk_base + REG_CLK_APBCLK1, 24); in ma35d1_clocks_probe()
968 clk_base + REG_CLK_APBCLK1, 25); in ma35d1_clocks_probe()
970 clk_base + REG_CLK_APBCLK1, 26); in ma35d1_clocks_probe()
972 hws[I2S0_MUX] = ma35d1_clk_mux(dev, "i2s0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
975 clk_base + REG_CLK_APBCLK2, 0); in ma35d1_clocks_probe()
976 hws[I2S1_MUX] = ma35d1_clk_mux(dev, "i2s1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
979 clk_base + REG_CLK_APBCLK2, 1); in ma35d1_clocks_probe()
982 clk_base + REG_CLK_APBCLK2, 2); in ma35d1_clocks_probe()
984 clk_base + REG_CLK_APBCLK2, 3); in ma35d1_clocks_probe()
986 hws[SPI0_MUX] = ma35d1_clk_mux(dev, "spi0_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
989 clk_base + REG_CLK_APBCLK2, 4); in ma35d1_clocks_probe()
990 hws[SPI1_MUX] = ma35d1_clk_mux(dev, "spi1_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
993 clk_base + REG_CLK_APBCLK2, 5); in ma35d1_clocks_probe()
994 hws[SPI2_MUX] = ma35d1_clk_mux(dev, "spi2_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
997 clk_base + REG_CLK_APBCLK2, 6); in ma35d1_clocks_probe()
998 hws[SPI3_MUX] = ma35d1_clk_mux(dev, "spi3_mux", clk_base + REG_CLK_CLKSEL4, in ma35d1_clocks_probe()
1001 clk_base + REG_CLK_APBCLK2, 7); in ma35d1_clocks_probe()
1004 clk_base + REG_CLK_APBCLK2, 8); in ma35d1_clocks_probe()
1006 clk_base + REG_CLK_APBCLK2, 9); in ma35d1_clocks_probe()
1008 clk_base + REG_CLK_APBCLK2, 10); in ma35d1_clocks_probe()
1011 clk_base + REG_CLK_APBCLK2, 12); in ma35d1_clocks_probe()
1013 clk_base + REG_CLK_APBCLK2, 13); in ma35d1_clocks_probe()
1015 clk_base + REG_CLK_APBCLK2, 14); in ma35d1_clocks_probe()
1019 clk_base + REG_CLK_CLKDIV4, in ma35d1_clocks_probe()
1022 clk_base + REG_CLK_APBCLK2, 24); in ma35d1_clocks_probe()
1025 clk_base + REG_CLK_CLKDIV4, in ma35d1_clocks_probe()
1028 clk_base + REG_CLK_APBCLK2, 25); in ma35d1_clocks_probe()