150 static void __iomem *clk_base;  variable
819 				clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra30_pll_init()
822 				clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,  in tegra30_pll_init()
828 				clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,  in tegra30_pll_init()
831 				clk_base + PLLM_OUT, 1, 0,  in tegra30_pll_init()
836 	clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
846 	clk = tegra_clk_register_pllu("pll_u", "pll_ref", clk_base, 0,  in tegra30_pll_init()
851 	clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
861 	clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,  in tegra30_pll_init()
874 			       clk_base + PLLE_AUX, 2, 1, 0, NULL);  in tegra30_pll_init()
897 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
906 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
915 				clk_base + SUPER_CCLKG_DIVIDER, 0,  in tegra30_super_clk_init()
923 				  clk_base + CCLKG_BURST_POLICY,  in tegra30_super_clk_init()
932 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
941 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
950 				clk_base + SUPER_CCLKLP_DIVIDER, 0,  in tegra30_super_clk_init()
958 				  clk_base + CCLKLP_BURST_POLICY,  in tegra30_super_clk_init()
968 	tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);  in tegra30_super_clk_init()
1007 	clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,  in tegra30_periph_clk_init()
1012 	clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,  in tegra30_periph_clk_init()
1017 	clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,  in tegra30_periph_clk_init()
1022 	clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, true);  in tegra30_periph_clk_init()
1026 	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,  in tegra30_periph_clk_init()
1031 	clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1036 	clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,  in tegra30_periph_clk_init()
1042 		clk = tegra_clk_register_periph_data(clk_base, data);  in tegra30_periph_clk_init()
1051 					clk_base, data->offset);  in tegra30_periph_clk_init()
1055 	tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);  in tegra30_periph_clk_init()
1064 		reg = readl(clk_base +  in tegra30_wait_cpu_in_reset()
1075 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);  in tegra30_put_cpu_in_reset()
1082 	       clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);  in tegra30_cpu_out_of_reset()
1089 	       clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);  in tegra30_enable_cpu_clock()
1090 	readl(clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);  in tegra30_enable_cpu_clock()
1097 	reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra30_disable_cpu_clock()
1099 	       clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);  in tegra30_disable_cpu_clock()
1108 	cpu_rst_status = readl(clk_base +  in tegra30_cpu_rail_off_ready()
1124 				readl(clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_suspend()
1125 	writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_suspend()
1128 				readl(clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_suspend()
1130 				readl(clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_suspend()
1132 				readl(clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_suspend()
1134 				readl(clk_base + CLK_RESET_CCLK_DIVIDER);  in tegra30_cpu_clock_suspend()
1143 	reg = readl(clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_resume()
1154 		misc = readl_relaxed(clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_resume()
1155 		base = readl_relaxed(clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_resume()
1161 						clk_base + CLK_RESET_PLLX_MISC);  in tegra30_cpu_clock_resume()
1163 						clk_base + CLK_RESET_PLLX_BASE);  in tegra30_cpu_clock_resume()
1176 					clk_base + CLK_RESET_CCLK_DIVIDER);  in tegra30_cpu_clock_resume()
1178 					clk_base + CLK_RESET_CCLK_BURST);  in tegra30_cpu_clock_resume()
1181 					clk_base + CLK_RESET_SOURCE_CSITE);  in tegra30_cpu_clock_resume()
1310 	clk_base = of_iomap(np, 0);  in tegra30_clock_init()
1311 	if (!clk_base) {  in tegra30_clock_init()
1329 	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,  in tegra30_clock_init()
1334 	if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,  in tegra30_clock_init()
1343 	tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,  in tegra30_clock_init()
1369 	clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,  in tegra30_car_probe()
1374 	clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,  in tegra30_car_probe()
1379 	clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,  in tegra30_car_probe()
1387 					   clk_base + SCLK_BURST_POLICY,  in tegra30_car_probe()