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/linux-6.12.1/arch/riscv/boot/dts/sophgo/
Dsg2042-cpus.dtsi257 compatible = "thead,c920", "riscv";
259 riscv,isa = "rv64imafdc";
260 riscv,isa-base = "rv64i";
261 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
272 mmu-type = "riscv,sv39";
275 compatible = "riscv,cpu-intc";
282 compatible = "thead,c920", "riscv";
284 riscv,isa = "rv64imafdc";
285 riscv,isa-base = "rv64i";
286 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
[all …]
Dcv18xx.dtsi21 compatible = "thead,c906", "riscv";
30 mmu-type = "riscv,sv39";
31 riscv,isa = "rv64imafdc";
32 riscv,isa-base = "rv64i";
33 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
37 compatible = "riscv,cpu-intc";
322 riscv,ndev = <101>;
/linux-6.12.1/drivers/gpu/drm/tegra/
Driscv.c32 static void riscv_writel(struct tegra_drm_riscv *riscv, u32 value, u32 offset) in riscv_writel() argument
34 writel(value, riscv->regs + offset); in riscv_writel()
37 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv) in tegra_drm_riscv_read_descriptors() argument
39 struct tegra_drm_riscv_descriptor *bl = &riscv->bl_desc; in tegra_drm_riscv_read_descriptors()
40 struct tegra_drm_riscv_descriptor *os = &riscv->os_desc; in tegra_drm_riscv_read_descriptors()
41 const struct device_node *np = riscv->dev->of_node; in tegra_drm_riscv_read_descriptors()
47 dev_err(riscv->dev, "failed to read " name ": %d\n", err); \ in tegra_drm_riscv_read_descriptors()
62 dev_err(riscv->dev, "descriptors not available\n"); in tegra_drm_riscv_read_descriptors()
69 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address, in tegra_drm_riscv_boot_bootrom() argument
76 riscv_writel(riscv, RISCV_BCR_CTRL_CORE_SELECT_RISCV, RISCV_BCR_CTRL); in tegra_drm_riscv_boot_bootrom()
[all …]
Driscv.h26 int tegra_drm_riscv_read_descriptors(struct tegra_drm_riscv *riscv);
27 int tegra_drm_riscv_boot_bootrom(struct tegra_drm_riscv *riscv, phys_addr_t image_address,
Dnvdec.c51 struct tegra_drm_riscv riscv; member
118 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1, in nvdec_boot_riscv()
119 &nvdec->riscv.bl_desc); in nvdec_boot_riscv()
135 err = tegra_drm_riscv_boot_bootrom(&nvdec->riscv, nvdec->carveout_base, 1, in nvdec_boot_riscv()
136 &nvdec->riscv.os_desc); in nvdec_boot_riscv()
500 nvdec->riscv.dev = dev; in nvdec_probe()
501 nvdec->riscv.regs = nvdec->regs; in nvdec_probe()
503 err = tegra_drm_riscv_read_descriptors(&nvdec->riscv); in nvdec_probe()
/linux-6.12.1/arch/riscv/
DMakefile68 riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima
69 riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima
70 riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd
71 riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c
72 riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v
82 riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei
87 KBUILD_CFLAGS += -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)fd([^v_]*)v?/\1\…
89 KBUILD_AFLAGS += -march=$(riscv-march-y)
92 CC_FLAGS_FPU := -march=$(shell echo $(riscv-march-y) | sed -E 's/(rv32ima|rv64ima)([^v_]*)v?/\1\2/…
109 KBUILD_CFLAGS += $(call cc-option,-mno-riscv-attribute)
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/linux-6.12.1/arch/riscv/boot/dts/sifive/
Dfu540-c000.dtsi26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 riscv,isa = "rv64imac";
33 riscv,isa-base = "rv64i";
34 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 mmu-type = "riscv,sv39";
58 riscv,isa = "rv64imafdc";
59 riscv,isa-base = "rv64i";
60 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
Dfu740-c000.dtsi26 compatible = "sifive,bullet0", "riscv";
33 riscv,isa = "rv64imac";
34 riscv,isa-base = "rv64i";
35 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 compatible = "riscv,cpu-intc";
45 compatible = "sifive,bullet0", "riscv";
57 mmu-type = "riscv,sv39";
60 riscv,isa = "rv64imafdc";
61 riscv,isa-base = "rv64i";
62 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux-6.12.1/arch/riscv/boot/dts/allwinner/
Dsun20i-d1s.dtsi15 compatible = "thead,c906", "riscv";
25 mmu-type = "riscv,sv39";
27 riscv,isa = "rv64imafdc";
28 riscv,isa-base = "rv64i";
29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
34 compatible = "riscv,cpu-intc";
73 riscv,ndev = <175>;
80 compatible = "riscv,pmu";
81 riscv,event-to-mhpmcounters =
92 riscv,event-to-mhpmevent =
[all …]
/linux-6.12.1/arch/riscv/boot/dts/microchip/
Dmpfs.dtsi19 compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 riscv,isa = "rv64imac";
26 riscv,isa-base = "rv64i";
27 riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 compatible = "riscv,cpu-intc";
40 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 mmu-type = "riscv,sv39";
54 riscv,isa = "rv64imafdc";
55 riscv,isa-base = "rv64i";
56 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux-6.12.1/arch/riscv/boot/dts/thead/
Dth1520.dtsi21 compatible = "thead,c910", "riscv";
23 riscv,isa = "rv64imafdc";
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
35 mmu-type = "riscv,sv39";
38 compatible = "riscv,cpu-intc";
45 compatible = "thead,c910", "riscv";
47 riscv,isa = "rv64imafdc";
48 riscv,isa-base = "rv64i";
49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux-6.12.1/arch/riscv/kernel/tests/
DKconfig.debug2 menu "arch/riscv/kernel Testing and Coverage"
8 bool "arch/riscv/kernel runtime Testing"
11 Enable riscv kernel runtime testing.
16 bool "KUnit test riscv module linking at runtime" if !KUNIT_ALL_TESTS
20 Enable this option to test riscv module linking at boot. This will
35 endmenu # "arch/riscv/kernel runtime Testing"
/linux-6.12.1/Documentation/arch/riscv/
Dacpi.rst9 "riscv-isa-release-1239329-2023-05-23" (commit 1239329
10 ) <https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-1239329-2023-05-23>`_
/linux-6.12.1/arch/riscv/boot/dts/renesas/
Dr9a07g043f.dtsi21 compatible = "andestech,ax45mp", "riscv";
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
42 compatible = "andestech,cpu-intc", "riscv,cpu-intc";
136 riscv,ndev = <511>;
/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7100.dtsi21 compatible = "sifive,u74-mc", "riscv";
34 mmu-type = "riscv,sv39";
36 riscv,isa = "rv64imafdc";
37 riscv,isa-base = "rv64i";
38 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
43 compatible = "riscv,cpu-intc";
50 compatible = "sifive,u74-mc", "riscv";
63 mmu-type = "riscv,sv39";
65 riscv,isa = "rv64imafdc";
66 riscv,isa-base = "rv64i";
[all …]
Djh7110.dtsi23 compatible = "sifive,s7", "riscv";
30 riscv,isa = "rv64imac_zba_zbb";
31 riscv,isa-base = "rv64i";
32 riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
37 compatible = "riscv,cpu-intc";
44 compatible = "sifive,u74-mc", "riscv";
57 mmu-type = "riscv,sv39";
59 riscv,isa = "rv64imafdc_zba_zbb";
60 riscv,isa-base = "rv64i";
61 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
[all …]
/linux-6.12.1/arch/riscv/purgatory/
DMakefile17 $(obj)/memcpy.o: $(srctree)/arch/riscv/lib/memcpy.S FORCE
20 $(obj)/memset.o: $(srctree)/arch/riscv/lib/memset.S FORCE
23 $(obj)/strcmp.o: $(srctree)/arch/riscv/lib/strcmp.S FORCE
26 $(obj)/strlen.o: $(srctree)/arch/riscv/lib/strlen.S FORCE
29 $(obj)/strncmp.o: $(srctree)/arch/riscv/lib/strncmp.S FORCE
/linux-6.12.1/arch/riscv/kernel/
DMakefile.syscalls3 syscall_abis_32 += riscv memfd_secret
4 syscall_abis_64 += riscv rlimit memfd_secret
Dvmlinux.lds.S25 OUTPUT_ARCH(riscv)
171 .riscv.attributes 0 : { *(.riscv.attributes) }
/linux-6.12.1/drivers/firmware/efi/
DMakefile38 riscv-obj-$(CONFIG_EFI) := efi-init.o riscv-runtime.o
39 obj-$(CONFIG_RISCV) += $(riscv-obj-y)
/linux-6.12.1/Documentation/translations/zh_CN/arch/riscv/
Dpatch-acceptance.rst5 :Original: Documentation/arch/riscv/patch-acceptance.rst
13 arch/riscv 开发者维护指南
/linux-6.12.1/drivers/irqchip/
DMakefile98 obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
99 obj-$(CONFIG_RISCV_APLIC) += irq-riscv-aplic-main.o irq-riscv-aplic-direct.o
100 obj-$(CONFIG_RISCV_APLIC_MSI) += irq-riscv-aplic-msi.o
101 obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platf…
/linux-6.12.1/arch/riscv/boot/dts/canaan/
Dk210.dtsi31 compatible = "canaan,k210", "riscv";
33 riscv,isa = "rv64imafdc";
34 mmu-type = "riscv,none";
42 compatible = "riscv,cpu-intc";
47 compatible = "canaan,k210", "riscv";
49 riscv,isa = "rv64imafdc";
50 mmu-type = "riscv,none";
58 compatible = "riscv,cpu-intc";
125 riscv,ndev = <65>;
/linux-6.12.1/scripts/
Dxz_wrap.sh99 riscv)
108 BCJ=--riscv
/linux-6.12.1/tools/scripts/
DMakefile.arch8 -e s/riscv.*/riscv/ -e s/loongarch.*/loongarch/)

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