dts/starfive/jh7110.dtsi

23 			compatible = "sifive,s7", "riscv";
30 			riscv,isa = "rv64imac_zba_zbb";
31 			riscv,isa-base = "rv64i";
32 			riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
37 				compatible = "riscv,cpu-intc";
44 			compatible = "sifive,u74-mc", "riscv";
57 			mmu-type = "riscv,sv39";
59 			riscv,isa = "rv64imafdc_zba_zbb";
60 			riscv,isa-base = "rv64i";
61 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
70 				compatible = "riscv,cpu-intc";
77 			compatible = "sifive,u74-mc", "riscv";
90 			mmu-type = "riscv,sv39";
92 			riscv,isa = "rv64imafdc_zba_zbb";
93 			riscv,isa-base = "rv64i";
94 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
103 				compatible = "riscv,cpu-intc";
110 			compatible = "sifive,u74-mc", "riscv";
123 			mmu-type = "riscv,sv39";
125 			riscv,isa = "rv64imafdc_zba_zbb";
126 			riscv,isa-base = "rv64i";
127 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
136 				compatible = "riscv,cpu-intc";
143 			compatible = "sifive,u74-mc", "riscv";
156 			mmu-type = "riscv,sv39";
158 			riscv,isa = "rv64imafdc_zba_zbb";
159 			riscv,isa-base = "rv64i";
160 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
169 				compatible = "riscv,cpu-intc";
386 			riscv,ndev = <136>;