dts/microchip/mpfs.dtsi

19 			compatible = "sifive,e51", "sifive,rocket0", "riscv";
25 			riscv,isa = "rv64imac";
26 			riscv,isa-base = "rv64i";
27 			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
34 				compatible = "riscv,cpu-intc";
40 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
52 			mmu-type = "riscv,sv39";
54 			riscv,isa = "rv64imafdc";
55 			riscv,isa-base = "rv64i";
56 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
65 				compatible = "riscv,cpu-intc";
71 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
83 			mmu-type = "riscv,sv39";
85 			riscv,isa = "rv64imafdc";
86 			riscv,isa-base = "rv64i";
87 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
96 				compatible = "riscv,cpu-intc";
102 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
114 			mmu-type = "riscv,sv39";
116 			riscv,isa = "rv64imafdc";
117 			riscv,isa-base = "rv64i";
118 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
127 				compatible = "riscv,cpu-intc";
133 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
145 			mmu-type = "riscv,sv39";
147 			riscv,isa = "rv64imafdc";
148 			riscv,isa-base = "rv64i";
149 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
157 				compatible = "riscv,cpu-intc";
242 			riscv,ndev = <186>;