dts/sifive/fu540-c000.dtsi

26 			compatible = "sifive,e51", "sifive,rocket0", "riscv";
32 			riscv,isa = "rv64imac";
33 			riscv,isa-base = "rv64i";
34 			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
39 				compatible = "riscv,cpu-intc";
44 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
56 			mmu-type = "riscv,sv39";
58 			riscv,isa = "rv64imafdc";
59 			riscv,isa-base = "rv64i";
60 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
66 				compatible = "riscv,cpu-intc";
71 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
83 			mmu-type = "riscv,sv39";
85 			riscv,isa = "rv64imafdc";
86 			riscv,isa-base = "rv64i";
87 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
93 				compatible = "riscv,cpu-intc";
98 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
110 			mmu-type = "riscv,sv39";
112 			riscv,isa = "rv64imafdc";
113 			riscv,isa-base = "rv64i";
114 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
120 				compatible = "riscv,cpu-intc";
125 			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
137 			mmu-type = "riscv,sv39";
139 			riscv,isa = "rv64imafdc";
140 			riscv,isa-base = "rv64i";
141 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
147 				compatible = "riscv,cpu-intc";
193 			riscv,ndev = <53>;