dts/sifive/fu740-c000.dtsi

26 			compatible = "sifive,bullet0", "riscv";
33 			riscv,isa = "rv64imac";
34 			riscv,isa-base = "rv64i";
35 			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
40 				compatible = "riscv,cpu-intc";
45 			compatible = "sifive,bullet0", "riscv";
57 			mmu-type = "riscv,sv39";
60 			riscv,isa = "rv64imafdc";
61 			riscv,isa-base = "rv64i";
62 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
67 				compatible = "riscv,cpu-intc";
72 			compatible = "sifive,bullet0", "riscv";
84 			mmu-type = "riscv,sv39";
87 			riscv,isa = "rv64imafdc";
88 			riscv,isa-base = "rv64i";
89 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
94 				compatible = "riscv,cpu-intc";
99 			compatible = "sifive,bullet0", "riscv";
111 			mmu-type = "riscv,sv39";
114 			riscv,isa = "rv64imafdc";
115 			riscv,isa-base = "rv64i";
116 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
121 				compatible = "riscv,cpu-intc";
126 			compatible = "sifive,bullet0", "riscv";
138 			mmu-type = "riscv,sv39";
141 			riscv,isa = "rv64imafdc";
142 			riscv,isa-base = "rv64i";
143 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
148 				compatible = "riscv,cpu-intc";
187 			riscv,ndev = <69>;