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Searched refs:REG_FPGA0_IQK (Results 1 – 8 of 8) sorted by relevance

/linux-6.12.1/drivers/net/wireless/realtek/rtl8xxxu/
D8723b.c585 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
587 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
622 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
625 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
658 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_iqk_path_a()
660 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_iqk_path_a()
695 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
697 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
732 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8723bu_rx_iqk_path_a()
735 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8723bu_rx_iqk_path_a()
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D8188f.c684 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_init_statistics()
686 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_init_statistics()
841 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
843 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
860 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
863 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
884 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_iqk_path_a()
886 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_iqk_path_a()
914 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188fu_rx_iqk_path_a()
916 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188fu_rx_iqk_path_a()
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D8710b.c832 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_init_statistics()
834 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_init_statistics()
1003 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_iqk_path_a()
1005 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1026 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_iqk_path_a()
1028 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1051 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_iqk_path_a()
1053 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_iqk_path_a()
1087 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8710bu_rx_iqk_path_a()
1089 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8710bu_rx_iqk_path_a()
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D8192e.c702 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_a()
710 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_a()
749 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); in rtl8192eu_rx_iqk_path_a()
767 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
802 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
812 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
829 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_rx_iqk_path_a()
855 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_rx_iqk_path_a()
875 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); in rtl8192eu_iqk_path_b()
883 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8192eu_iqk_path_b()
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D8192f.c808 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_a()
826 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_iqk_path_a()
861 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_a()
897 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
906 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_rx_iqk_path_a()
947 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
959 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
976 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000); in rtl8192fu_rx_iqk_path_a()
1010 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_rx_iqk_path_a()
1032 rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0); in rtl8192fu_iqk_path_b()
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D8188e.c650 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
652 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
661 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
663 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
702 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
704 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
712 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_rx_iqk_path_a()
714 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_rx_iqk_path_a()
834 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); in rtl8188eu_phy_iqcalibrate()
836 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); in rtl8188eu_phy_iqcalibrate()
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Dregs.h1145 #define REG_FPGA0_IQK 0x0e28 macro
Dcore.c3255 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8xxxu_phy_iqcalibrate()
3296 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); in rtl8xxxu_phy_iqcalibrate()
3298 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); in rtl8xxxu_phy_iqcalibrate()
3329 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); in rtl8xxxu_phy_iqcalibrate()