702 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_iqk_path_a()
710 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_iqk_path_a()
749 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);  in rtl8192eu_rx_iqk_path_a()
767 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_rx_iqk_path_a()
802 		rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_rx_iqk_path_a()
812 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_rx_iqk_path_a()
829 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_rx_iqk_path_a()
855 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_rx_iqk_path_a()
875 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_iqk_path_b()
883 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_iqk_path_b()
925 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_rx_iqk_path_b()
943 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_rx_iqk_path_b()
981 		rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_rx_iqk_path_b()
991 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_rx_iqk_path_b()
1008 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_rx_iqk_path_b()
1035 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_rx_iqk_path_b()
1118 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_phy_iqcalibrate()
1158 		rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_phy_iqcalibrate()
1160 		rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_phy_iqcalibrate()
1165 		rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);  in rtl8192eu_phy_iqcalibrate()
1201 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);  in rtl8192eu_phy_iqcalibrate()