808 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_iqk_path_a()
826 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_iqk_path_a()
861 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_iqk_path_a()
897 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_a()
906 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_rx_iqk_path_a()
947 		rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_a()
959 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_a()
976 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_rx_iqk_path_a()
1010 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_a()
1032 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_iqk_path_b()
1051 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_iqk_path_b()
1086 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_iqk_path_b()
1125 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_b()
1140 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_rx_iqk_path_b()
1177 		rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_b()
1189 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_b()
1204 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_rx_iqk_path_b()
1237 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_rx_iqk_path_b()
1283 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_phy_iqcalibrate()
1329 		rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x000000);  in rtl8192fu_phy_iqcalibrate()
1331 		rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0x808000);  in rtl8192fu_phy_iqcalibrate()
1407 	rtl8xxxu_write32_mask(priv, REG_FPGA0_IQK, 0xffffff00, 0);  in rtl8192fu_phy_iqcalibrate()