Lines Matching refs:REG_FPGA0_IQK

650 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_rx_iqk_path_a()
652 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);  in rtl8188eu_rx_iqk_path_a()
661 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_rx_iqk_path_a()
663 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);  in rtl8188eu_rx_iqk_path_a()
702 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_rx_iqk_path_a()
704 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);  in rtl8188eu_rx_iqk_path_a()
712 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_rx_iqk_path_a()
714 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);  in rtl8188eu_rx_iqk_path_a()
834 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_phy_iqcalibrate()
836 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);  in rtl8188eu_phy_iqcalibrate()
874 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_phy_iqcalibrate()
876 	rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);  in rtl8188eu_phy_iqcalibrate()