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/linux-6.12.1/arch/sh/kernel/cpu/sh4/
Dperf_event.c84 #define C(x) PERF_COUNT_HW_CACHE_##x macro
91 [ C(L1D) ] = {
92 [ C(OP_READ) ] = {
93 [ C(RESULT_ACCESS) ] = 0x0001,
94 [ C(RESULT_MISS) ] = 0x0004,
96 [ C(OP_WRITE) ] = {
97 [ C(RESULT_ACCESS) ] = 0x0002,
98 [ C(RESULT_MISS) ] = 0x0005,
100 [ C(OP_PREFETCH) ] = {
101 [ C(RESULT_ACCESS) ] = 0,
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh4a/
Dperf_event.c109 #define C(x) PERF_COUNT_HW_CACHE_##x macro
116 [ C(L1D) ] = {
117 [ C(OP_READ) ] = {
118 [ C(RESULT_ACCESS) ] = 0x0031,
119 [ C(RESULT_MISS) ] = 0x0032,
121 [ C(OP_WRITE) ] = {
122 [ C(RESULT_ACCESS) ] = 0x0039,
123 [ C(RESULT_MISS) ] = 0x003a,
125 [ C(OP_PREFETCH) ] = {
126 [ C(RESULT_ACCESS) ] = 0,
[all …]
/linux-6.12.1/arch/x86/events/zhaoxin/
Dcore.c51 [C(L1D)] = {
52 [C(OP_READ)] = {
53 [C(RESULT_ACCESS)] = 0x0042,
54 [C(RESULT_MISS)] = 0x0538,
56 [C(OP_WRITE)] = {
57 [C(RESULT_ACCESS)] = 0x0043,
58 [C(RESULT_MISS)] = 0x0562,
60 [C(OP_PREFETCH)] = {
61 [C(RESULT_ACCESS)] = -1,
62 [C(RESULT_MISS)] = -1,
[all …]
/linux-6.12.1/arch/powerpc/perf/
Dpower10-pmu.c351 #define C(x) PERF_COUNT_HW_CACHE_##x macro
358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
359 [C(L1D)] = {
360 [C(OP_READ)] = {
361 [C(RESULT_ACCESS)] = PM_LD_REF_L1,
362 [C(RESULT_MISS)] = PM_LD_MISS_L1,
364 [C(OP_WRITE)] = {
365 [C(RESULT_ACCESS)] = 0,
366 [C(RESULT_MISS)] = PM_ST_MISS_L1,
368 [C(OP_PREFETCH)] = {
[all …]
Dgeneric-compat-pmu.c178 #define C(x) PERF_COUNT_HW_CACHE_##x macro
185 static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
186 [ C(L1D) ] = {
187 [ C(OP_READ) ] = {
188 [ C(RESULT_ACCESS) ] = 0,
189 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
191 [ C(OP_WRITE) ] = {
192 [ C(RESULT_ACCESS) ] = 0,
193 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
195 [ C(OP_PREFETCH) ] = {
[all …]
Dpower8-pmu.c259 #define C(x) PERF_COUNT_HW_CACHE_##x macro
266 static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
267 [ C(L1D) ] = {
268 [ C(OP_READ) ] = {
269 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
270 [ C(RESULT_MISS) ] = PM_LD_MISS_L1,
272 [ C(OP_WRITE) ] = {
273 [ C(RESULT_ACCESS) ] = 0,
274 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
276 [ C(OP_PREFETCH) ] = {
[all …]
Dpower9-pmu.c330 #define C(x) PERF_COUNT_HW_CACHE_##x macro
337 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
338 [ C(L1D) ] = {
339 [ C(OP_READ) ] = {
340 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
341 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
343 [ C(OP_WRITE) ] = {
344 [ C(RESULT_ACCESS) ] = 0,
345 [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
347 [ C(OP_PREFETCH) ] = {
[all …]
De6500-pmu.c28 #define C(x) PERF_COUNT_HW_CACHE_##x macro
35 static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
36 [C(L1D)] = {
38 [C(OP_READ)] = { 27, 222 },
39 [C(OP_WRITE)] = { 28, 223 },
40 [C(OP_PREFETCH)] = { 29, 0 },
42 [C(L1I)] = {
44 [C(OP_READ)] = { 2, 254 },
45 [C(OP_WRITE)] = { -1, -1 },
46 [C(OP_PREFETCH)] = { 37, 0 },
[all …]
De500-pmu.c27 #define C(x) PERF_COUNT_HW_CACHE_##x macro
34 static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
39 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
40 [C(OP_READ)] = { 27, 0 },
41 [C(OP_WRITE)] = { 28, 0 },
42 [C(OP_PREFETCH)] = { 29, 0 },
44 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
45 [C(OP_READ)] = { 2, 60 },
46 [C(OP_WRITE)] = { -1, -1 },
47 [C(OP_PREFETCH)] = { 0, 0 },
[all …]
/linux-6.12.1/drivers/perf/
Darm_v7_pmu.c177 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
178 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
179 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS,
180 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL,
182 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
183 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
185 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
186 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
187 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
188 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
[all …]
Driscv_pmu_sbi.c155 #define C(x) PERF_COUNT_HW_CACHE_##x macro
159 [C(L1D)] = {
160 [C(OP_READ)] = {
161 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
162 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
163 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS),
164 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
166 [C(OP_WRITE)] = {
167 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS),
168 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}},
[all …]
Darm_pmuv3.c60 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
61 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
63 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
64 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
66 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
67 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
69 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
70 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
72 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
73 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
[all …]
/linux-6.12.1/arch/x86/events/intel/
Dp6.c28 [ C(L1D) ] = {
29 [ C(OP_READ) ] = {
30 [ C(RESULT_ACCESS) ] = 0x0043, /* DATA_MEM_REFS */
31 [ C(RESULT_MISS) ] = 0x0045, /* DCU_LINES_IN */
33 [ C(OP_WRITE) ] = {
34 [ C(RESULT_ACCESS) ] = 0,
35 [ C(RESULT_MISS) ] = 0x0f29, /* L2_LD:M:E:S:I */
37 [ C(OP_PREFETCH) ] = {
38 [ C(RESULT_ACCESS) ] = 0,
39 [ C(RESULT_MISS) ] = 0,
[all …]
Dknc.c26 [ C(L1D) ] = {
27 [ C(OP_READ) ] = {
32 [ C(RESULT_ACCESS) ] = ARCH_PERFMON_EVENTSEL_INT,
34 [ C(RESULT_MISS) ] = 0x0003, /* DATA_READ_MISS */
36 [ C(OP_WRITE) ] = {
37 [ C(RESULT_ACCESS) ] = 0x0001, /* DATA_WRITE */
38 [ C(RESULT_MISS) ] = 0x0004, /* DATA_WRITE_MISS */
40 [ C(OP_PREFETCH) ] = {
41 [ C(RESULT_ACCESS) ] = 0x0011, /* L1_DATA_PF1 */
42 [ C(RESULT_MISS) ] = 0x001c, /* L1_DATA_PF1_MISS */
[all …]
Dcore.c551 [ C(L1D ) ] = {
552 [ C(OP_READ) ] = {
553 [ C(RESULT_ACCESS) ] = 0x81d0,
554 [ C(RESULT_MISS) ] = 0xe124,
556 [ C(OP_WRITE) ] = {
557 [ C(RESULT_ACCESS) ] = 0x82d0,
560 [ C(L1I ) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_MISS) ] = 0xe424,
564 [ C(OP_WRITE) ] = {
[all …]
/linux-6.12.1/tools/testing/selftests/bpf/progs/
Dtest_verif_scale2.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
Dtest_verif_scale3.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
Dtest_verif_scale1.c20 #define C do { \ in balancer_ingress() macro
26 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
Dcore_kern.c85 #define C do { \ in balancer_ingress() macro
99 #define C30 C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C;C; in balancer_ingress()
/linux-6.12.1/arch/sparc/kernel/
Dperf_event.c147 #define C(x) PERF_COUNT_HW_CACHE_##x macro
221 [C(L1D)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
224 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
226 [C(OP_WRITE)] = {
227 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
228 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
230 [C(OP_PREFETCH)] = {
231 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
[all …]
/linux-6.12.1/arch/mips/kernel/
Dperf_event_mipsxx.c74 #define C(x) PERF_COUNT_HW_CACHE_##x macro
1010 [C(L1D)] = {
1017 [C(OP_READ)] = {
1018 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1019 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1021 [C(OP_WRITE)] = {
1022 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1023 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1026 [C(L1I)] = {
1027 [C(OP_READ)] = {
[all …]
/linux-6.12.1/arch/x86/events/amd/
Dcore.c31 [ C(L1D) ] = {
32 [ C(OP_READ) ] = {
33 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
34 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
36 [ C(OP_WRITE) ] = {
37 [ C(RESULT_ACCESS) ] = 0,
38 [ C(RESULT_MISS) ] = 0,
40 [ C(OP_PREFETCH) ] = {
41 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
42 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
[all …]
/linux-6.12.1/kernel/trace/
Dtrace_probe.h471 C(FILE_NOT_FOUND, "Failed to find the given file"), \
472 C(NO_REGULAR_FILE, "Not a regular file"), \
473 C(BAD_REFCNT, "Invalid reference counter offset"), \
474 C(REFCNT_OPEN_BRACE, "Reference counter brace is not closed"), \
475 C(BAD_REFCNT_SUFFIX, "Reference counter has wrong suffix"), \
476 C(BAD_UPROBE_OFFS, "Invalid uprobe offset"), \
477 C(BAD_MAXACT_TYPE, "Maxactive is only for function exit"), \
478 C(BAD_MAXACT, "Invalid maxactive number"), \
479 C(MAXACT_TOO_BIG, "Maxactive is too big"), \
480 C(BAD_PROBE_ADDR, "Invalid probed address or symbol"), \
[all …]
/linux-6.12.1/lib/zstd/common/
Dcpu.h97 #define C(name, bit) X(name, f1c, bit) macro
98 C(sse3, 0)
99 C(pclmuldq, 1)
100 C(dtes64, 2)
101 C(monitor, 3)
102 C(dscpl, 4)
103 C(vmx, 5)
104 C(smx, 6)
105 C(eist, 7)
106 C(tm2, 8)
[all …]
/linux-6.12.1/lib/crypto/
Dsha1.c57 #define SHA_ROUND(t, input, fn, constant, A, B, C, D, E) do { \ argument
61 TEMP = E; E = D; D = C; C = B; B = A; A = TEMP; } while (0)
63 #define T_0_15(t, A, B, C, D, E) SHA_ROUND(t, SHA_SRC, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
64 #define T_16_19(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (((C^D)&B)^D) , 0x5a827999, A, B, C, D, E ) argument
65 #define T_20_39(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0x6ed9eba1, A, B, C, D, E ) argument
66 #define T_40_59(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, ((B&C)+(D&(B^C))) , 0x8f1bbcdc, A, B, C, D,… argument
67 #define T_60_79(t, A, B, C, D, E) SHA_ROUND(t, SHA_MIX, (B^C^D) , 0xca62c1d6, A, B, C, D, E ) argument
89 __u32 A, B, C, D, E; in sha1_transform() local
94 C = digest[2]; in sha1_transform()
100 T_0_15(i, A, B, C, D, E); in sha1_transform()
[all …]

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