Lines Matching refs:C
31 [ C(L1D) ] = {
32 [ C(OP_READ) ] = {
33 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
34 [ C(RESULT_MISS) ] = 0x0141, /* Data Cache Misses */
36 [ C(OP_WRITE) ] = {
37 [ C(RESULT_ACCESS) ] = 0,
38 [ C(RESULT_MISS) ] = 0,
40 [ C(OP_PREFETCH) ] = {
41 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts */
42 [ C(RESULT_MISS) ] = 0x0167, /* Data Prefetcher :cancelled */
45 [ C(L1I ) ] = {
46 [ C(OP_READ) ] = {
47 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches */
48 [ C(RESULT_MISS) ] = 0x0081, /* Instruction cache misses */
50 [ C(OP_WRITE) ] = {
51 [ C(RESULT_ACCESS) ] = -1,
52 [ C(RESULT_MISS) ] = -1,
54 [ C(OP_PREFETCH) ] = {
55 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
56 [ C(RESULT_MISS) ] = 0,
59 [ C(LL ) ] = {
60 [ C(OP_READ) ] = {
61 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
62 [ C(RESULT_MISS) ] = 0x037E, /* L2 Cache Misses : IC+DC */
64 [ C(OP_WRITE) ] = {
65 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback */
66 [ C(RESULT_MISS) ] = 0,
68 [ C(OP_PREFETCH) ] = {
69 [ C(RESULT_ACCESS) ] = 0,
70 [ C(RESULT_MISS) ] = 0,
73 [ C(DTLB) ] = {
74 [ C(OP_READ) ] = {
75 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses */
76 [ C(RESULT_MISS) ] = 0x0746, /* L1_DTLB_AND_L2_DLTB_MISS.ALL */
78 [ C(OP_WRITE) ] = {
79 [ C(RESULT_ACCESS) ] = 0,
80 [ C(RESULT_MISS) ] = 0,
82 [ C(OP_PREFETCH) ] = {
83 [ C(RESULT_ACCESS) ] = 0,
84 [ C(RESULT_MISS) ] = 0,
87 [ C(ITLB) ] = {
88 [ C(OP_READ) ] = {
89 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes */
90 [ C(RESULT_MISS) ] = 0x0385, /* L1_ITLB_AND_L2_ITLB_MISS.ALL */
92 [ C(OP_WRITE) ] = {
93 [ C(RESULT_ACCESS) ] = -1,
94 [ C(RESULT_MISS) ] = -1,
96 [ C(OP_PREFETCH) ] = {
97 [ C(RESULT_ACCESS) ] = -1,
98 [ C(RESULT_MISS) ] = -1,
101 [ C(BPU ) ] = {
102 [ C(OP_READ) ] = {
103 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr. */
104 [ C(RESULT_MISS) ] = 0x00c3, /* Retired Mispredicted BI */
106 [ C(OP_WRITE) ] = {
107 [ C(RESULT_ACCESS) ] = -1,
108 [ C(RESULT_MISS) ] = -1,
110 [ C(OP_PREFETCH) ] = {
111 [ C(RESULT_ACCESS) ] = -1,
112 [ C(RESULT_MISS) ] = -1,
115 [ C(NODE) ] = {
116 [ C(OP_READ) ] = {
117 [ C(RESULT_ACCESS) ] = 0xb8e9, /* CPU Request to Memory, l+r */
118 [ C(RESULT_MISS) ] = 0x98e9, /* CPU Request to Memory, r */
120 [ C(OP_WRITE) ] = {
121 [ C(RESULT_ACCESS) ] = -1,
122 [ C(RESULT_MISS) ] = -1,
124 [ C(OP_PREFETCH) ] = {
125 [ C(RESULT_ACCESS) ] = -1,
126 [ C(RESULT_MISS) ] = -1,
135 [C(L1D)] = {
136 [C(OP_READ)] = {
137 [C(RESULT_ACCESS)] = 0x0040, /* Data Cache Accesses */
138 [C(RESULT_MISS)] = 0xc860, /* L2$ access from DC Miss */
140 [C(OP_WRITE)] = {
141 [C(RESULT_ACCESS)] = 0,
142 [C(RESULT_MISS)] = 0,
144 [C(OP_PREFETCH)] = {
145 [C(RESULT_ACCESS)] = 0xff5a, /* h/w prefetch DC Fills */
146 [C(RESULT_MISS)] = 0,
149 [C(L1I)] = {
150 [C(OP_READ)] = {
151 [C(RESULT_ACCESS)] = 0x0080, /* Instruction cache fetches */
152 [C(RESULT_MISS)] = 0x0081, /* Instruction cache misses */
154 [C(OP_WRITE)] = {
155 [C(RESULT_ACCESS)] = -1,
156 [C(RESULT_MISS)] = -1,
158 [C(OP_PREFETCH)] = {
159 [C(RESULT_ACCESS)] = 0,
160 [C(RESULT_MISS)] = 0,
163 [C(LL)] = {
164 [C(OP_READ)] = {
165 [C(RESULT_ACCESS)] = 0,
166 [C(RESULT_MISS)] = 0,
168 [C(OP_WRITE)] = {
169 [C(RESULT_ACCESS)] = 0,
170 [C(RESULT_MISS)] = 0,
172 [C(OP_PREFETCH)] = {
173 [C(RESULT_ACCESS)] = 0,
174 [C(RESULT_MISS)] = 0,
177 [C(DTLB)] = {
178 [C(OP_READ)] = {
179 [C(RESULT_ACCESS)] = 0xff45, /* All L2 DTLB accesses */
180 [C(RESULT_MISS)] = 0xf045, /* L2 DTLB misses (PT walks) */
182 [C(OP_WRITE)] = {
183 [C(RESULT_ACCESS)] = 0,
184 [C(RESULT_MISS)] = 0,
186 [C(OP_PREFETCH)] = {
187 [C(RESULT_ACCESS)] = 0,
188 [C(RESULT_MISS)] = 0,
191 [C(ITLB)] = {
192 [C(OP_READ)] = {
193 [C(RESULT_ACCESS)] = 0x0084, /* L1 ITLB misses, L2 ITLB hits */
194 [C(RESULT_MISS)] = 0xff85, /* L1 ITLB misses, L2 misses */
196 [C(OP_WRITE)] = {
197 [C(RESULT_ACCESS)] = -1,
198 [C(RESULT_MISS)] = -1,
200 [C(OP_PREFETCH)] = {
201 [C(RESULT_ACCESS)] = -1,
202 [C(RESULT_MISS)] = -1,
205 [C(BPU)] = {
206 [C(OP_READ)] = {
207 [C(RESULT_ACCESS)] = 0x00c2, /* Retired Branch Instr. */
208 [C(RESULT_MISS)] = 0x00c3, /* Retired Mispredicted BI */
210 [C(OP_WRITE)] = {
211 [C(RESULT_ACCESS)] = -1,
212 [C(RESULT_MISS)] = -1,
214 [C(OP_PREFETCH)] = {
215 [C(RESULT_ACCESS)] = -1,
216 [C(RESULT_MISS)] = -1,
219 [C(NODE)] = {
220 [C(OP_READ)] = {
221 [C(RESULT_ACCESS)] = 0,
222 [C(RESULT_MISS)] = 0,
224 [C(OP_WRITE)] = {
225 [C(RESULT_ACCESS)] = -1,
226 [C(RESULT_MISS)] = -1,
228 [C(OP_PREFETCH)] = {
229 [C(RESULT_ACCESS)] = -1,
230 [C(RESULT_MISS)] = -1,