Lines Matching refs:C
551 [ C(L1D ) ] = {
552 [ C(OP_READ) ] = {
553 [ C(RESULT_ACCESS) ] = 0x81d0,
554 [ C(RESULT_MISS) ] = 0xe124,
556 [ C(OP_WRITE) ] = {
557 [ C(RESULT_ACCESS) ] = 0x82d0,
560 [ C(L1I ) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_MISS) ] = 0xe424,
564 [ C(OP_WRITE) ] = {
565 [ C(RESULT_ACCESS) ] = -1,
566 [ C(RESULT_MISS) ] = -1,
569 [ C(LL ) ] = {
570 [ C(OP_READ) ] = {
571 [ C(RESULT_ACCESS) ] = 0x12a,
572 [ C(RESULT_MISS) ] = 0x12a,
574 [ C(OP_WRITE) ] = {
575 [ C(RESULT_ACCESS) ] = 0x12a,
576 [ C(RESULT_MISS) ] = 0x12a,
579 [ C(DTLB) ] = {
580 [ C(OP_READ) ] = {
581 [ C(RESULT_ACCESS) ] = 0x81d0,
582 [ C(RESULT_MISS) ] = 0xe12,
584 [ C(OP_WRITE) ] = {
585 [ C(RESULT_ACCESS) ] = 0x82d0,
586 [ C(RESULT_MISS) ] = 0xe13,
589 [ C(ITLB) ] = {
590 [ C(OP_READ) ] = {
591 [ C(RESULT_ACCESS) ] = -1,
592 [ C(RESULT_MISS) ] = 0xe11,
594 [ C(OP_WRITE) ] = {
595 [ C(RESULT_ACCESS) ] = -1,
596 [ C(RESULT_MISS) ] = -1,
598 [ C(OP_PREFETCH) ] = {
599 [ C(RESULT_ACCESS) ] = -1,
600 [ C(RESULT_MISS) ] = -1,
603 [ C(BPU ) ] = {
604 [ C(OP_READ) ] = {
605 [ C(RESULT_ACCESS) ] = 0x4c4,
606 [ C(RESULT_MISS) ] = 0x4c5,
608 [ C(OP_WRITE) ] = {
609 [ C(RESULT_ACCESS) ] = -1,
610 [ C(RESULT_MISS) ] = -1,
612 [ C(OP_PREFETCH) ] = {
613 [ C(RESULT_ACCESS) ] = -1,
614 [ C(RESULT_MISS) ] = -1,
617 [ C(NODE) ] = {
618 [ C(OP_READ) ] = {
619 [ C(RESULT_ACCESS) ] = 0x12a,
620 [ C(RESULT_MISS) ] = 0x12a,
630 [ C(LL ) ] = {
631 [ C(OP_READ) ] = {
632 [ C(RESULT_ACCESS) ] = 0x10001,
633 [ C(RESULT_MISS) ] = 0x3fbfc00001,
635 [ C(OP_WRITE) ] = {
636 [ C(RESULT_ACCESS) ] = 0x3f3ffc0002,
637 [ C(RESULT_MISS) ] = 0x3f3fc00002,
640 [ C(NODE) ] = {
641 [ C(OP_READ) ] = {
642 [ C(RESULT_ACCESS) ] = 0x10c000001,
643 [ C(RESULT_MISS) ] = 0x3fb3000001,
697 [ C(L1D ) ] = {
698 [ C(OP_READ) ] = {
699 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
700 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
702 [ C(OP_WRITE) ] = {
703 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
704 [ C(RESULT_MISS) ] = 0x0,
706 [ C(OP_PREFETCH) ] = {
707 [ C(RESULT_ACCESS) ] = 0x0,
708 [ C(RESULT_MISS) ] = 0x0,
711 [ C(L1I ) ] = {
712 [ C(OP_READ) ] = {
713 [ C(RESULT_ACCESS) ] = 0x0,
714 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
716 [ C(OP_WRITE) ] = {
717 [ C(RESULT_ACCESS) ] = -1,
718 [ C(RESULT_MISS) ] = -1,
720 [ C(OP_PREFETCH) ] = {
721 [ C(RESULT_ACCESS) ] = 0x0,
722 [ C(RESULT_MISS) ] = 0x0,
725 [ C(LL ) ] = {
726 [ C(OP_READ) ] = {
727 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
728 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
730 [ C(OP_WRITE) ] = {
731 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
732 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
734 [ C(OP_PREFETCH) ] = {
735 [ C(RESULT_ACCESS) ] = 0x0,
736 [ C(RESULT_MISS) ] = 0x0,
739 [ C(DTLB) ] = {
740 [ C(OP_READ) ] = {
741 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
742 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
744 [ C(OP_WRITE) ] = {
745 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
746 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
748 [ C(OP_PREFETCH) ] = {
749 [ C(RESULT_ACCESS) ] = 0x0,
750 [ C(RESULT_MISS) ] = 0x0,
753 [ C(ITLB) ] = {
754 [ C(OP_READ) ] = {
755 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
756 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
758 [ C(OP_WRITE) ] = {
759 [ C(RESULT_ACCESS) ] = -1,
760 [ C(RESULT_MISS) ] = -1,
762 [ C(OP_PREFETCH) ] = {
763 [ C(RESULT_ACCESS) ] = -1,
764 [ C(RESULT_MISS) ] = -1,
767 [ C(BPU ) ] = {
768 [ C(OP_READ) ] = {
769 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
770 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
772 [ C(OP_WRITE) ] = {
773 [ C(RESULT_ACCESS) ] = -1,
774 [ C(RESULT_MISS) ] = -1,
776 [ C(OP_PREFETCH) ] = {
777 [ C(RESULT_ACCESS) ] = -1,
778 [ C(RESULT_MISS) ] = -1,
781 [ C(NODE) ] = {
782 [ C(OP_READ) ] = {
783 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
784 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
786 [ C(OP_WRITE) ] = {
787 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
788 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
790 [ C(OP_PREFETCH) ] = {
791 [ C(RESULT_ACCESS) ] = 0x0,
792 [ C(RESULT_MISS) ] = 0x0,
802 [ C(LL ) ] = {
803 [ C(OP_READ) ] = {
804 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
806 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
810 [ C(OP_WRITE) ] = {
811 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
813 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
817 [ C(OP_PREFETCH) ] = {
818 [ C(RESULT_ACCESS) ] = 0x0,
819 [ C(RESULT_MISS) ] = 0x0,
822 [ C(NODE) ] = {
823 [ C(OP_READ) ] = {
824 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
826 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
829 [ C(OP_WRITE) ] = {
830 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
832 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
835 [ C(OP_PREFETCH) ] = {
836 [ C(RESULT_ACCESS) ] = 0x0,
837 [ C(RESULT_MISS) ] = 0x0,
890 [ C(LL ) ] = {
891 [ C(OP_READ) ] = {
892 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
893 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
895 [ C(OP_WRITE) ] = {
896 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
897 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
899 [ C(OP_PREFETCH) ] = {
900 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
901 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
904 [ C(NODE) ] = {
905 [ C(OP_READ) ] = {
906 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
907 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
909 [ C(OP_WRITE) ] = {
910 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
911 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
913 [ C(OP_PREFETCH) ] = {
914 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
915 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
925 [ C(L1D) ] = {
926 [ C(OP_READ) ] = {
927 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
928 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
930 [ C(OP_WRITE) ] = {
931 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
932 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
934 [ C(OP_PREFETCH) ] = {
935 [ C(RESULT_ACCESS) ] = 0x0,
936 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
939 [ C(L1I ) ] = {
940 [ C(OP_READ) ] = {
941 [ C(RESULT_ACCESS) ] = 0x0,
942 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
944 [ C(OP_WRITE) ] = {
945 [ C(RESULT_ACCESS) ] = -1,
946 [ C(RESULT_MISS) ] = -1,
948 [ C(OP_PREFETCH) ] = {
949 [ C(RESULT_ACCESS) ] = 0x0,
950 [ C(RESULT_MISS) ] = 0x0,
953 [ C(LL ) ] = {
954 [ C(OP_READ) ] = {
956 [ C(RESULT_ACCESS) ] = 0x01b7,
958 [ C(RESULT_MISS) ] = 0x01b7,
960 [ C(OP_WRITE) ] = {
962 [ C(RESULT_ACCESS) ] = 0x01b7,
964 [ C(RESULT_MISS) ] = 0x01b7,
966 [ C(OP_PREFETCH) ] = {
968 [ C(RESULT_ACCESS) ] = 0x01b7,
970 [ C(RESULT_MISS) ] = 0x01b7,
973 [ C(DTLB) ] = {
974 [ C(OP_READ) ] = {
975 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
976 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
978 [ C(OP_WRITE) ] = {
979 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
980 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
982 [ C(OP_PREFETCH) ] = {
983 [ C(RESULT_ACCESS) ] = 0x0,
984 [ C(RESULT_MISS) ] = 0x0,
987 [ C(ITLB) ] = {
988 [ C(OP_READ) ] = {
989 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
990 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
992 [ C(OP_WRITE) ] = {
993 [ C(RESULT_ACCESS) ] = -1,
994 [ C(RESULT_MISS) ] = -1,
996 [ C(OP_PREFETCH) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
1001 [ C(BPU ) ] = {
1002 [ C(OP_READ) ] = {
1003 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1004 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1006 [ C(OP_WRITE) ] = {
1007 [ C(RESULT_ACCESS) ] = -1,
1008 [ C(RESULT_MISS) ] = -1,
1010 [ C(OP_PREFETCH) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1015 [ C(NODE) ] = {
1016 [ C(OP_READ) ] = {
1017 [ C(RESULT_ACCESS) ] = 0x01b7,
1018 [ C(RESULT_MISS) ] = 0x01b7,
1020 [ C(OP_WRITE) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1024 [ C(OP_PREFETCH) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1081 [ C(L1D ) ] = {
1082 [ C(OP_READ) ] = {
1083 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1084 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
1086 [ C(OP_WRITE) ] = {
1087 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1088 [ C(RESULT_MISS) ] = 0x0,
1090 [ C(OP_PREFETCH) ] = {
1091 [ C(RESULT_ACCESS) ] = 0x0,
1092 [ C(RESULT_MISS) ] = 0x0,
1095 [ C(L1I ) ] = {
1096 [ C(OP_READ) ] = {
1097 [ C(RESULT_ACCESS) ] = 0x0,
1098 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
1100 [ C(OP_WRITE) ] = {
1101 [ C(RESULT_ACCESS) ] = -1,
1102 [ C(RESULT_MISS) ] = -1,
1104 [ C(OP_PREFETCH) ] = {
1105 [ C(RESULT_ACCESS) ] = 0x0,
1106 [ C(RESULT_MISS) ] = 0x0,
1109 [ C(LL ) ] = {
1110 [ C(OP_READ) ] = {
1111 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1112 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1114 [ C(OP_WRITE) ] = {
1115 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1116 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1118 [ C(OP_PREFETCH) ] = {
1119 [ C(RESULT_ACCESS) ] = 0x0,
1120 [ C(RESULT_MISS) ] = 0x0,
1123 [ C(DTLB) ] = {
1124 [ C(OP_READ) ] = {
1125 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1126 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
1128 [ C(OP_WRITE) ] = {
1129 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1130 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
1132 [ C(OP_PREFETCH) ] = {
1133 [ C(RESULT_ACCESS) ] = 0x0,
1134 [ C(RESULT_MISS) ] = 0x0,
1137 [ C(ITLB) ] = {
1138 [ C(OP_READ) ] = {
1139 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
1140 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
1142 [ C(OP_WRITE) ] = {
1143 [ C(RESULT_ACCESS) ] = -1,
1144 [ C(RESULT_MISS) ] = -1,
1146 [ C(OP_PREFETCH) ] = {
1147 [ C(RESULT_ACCESS) ] = -1,
1148 [ C(RESULT_MISS) ] = -1,
1151 [ C(BPU ) ] = {
1152 [ C(OP_READ) ] = {
1153 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
1154 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1156 [ C(OP_WRITE) ] = {
1157 [ C(RESULT_ACCESS) ] = -1,
1158 [ C(RESULT_MISS) ] = -1,
1160 [ C(OP_PREFETCH) ] = {
1161 [ C(RESULT_ACCESS) ] = -1,
1162 [ C(RESULT_MISS) ] = -1,
1165 [ C(NODE) ] = {
1166 [ C(OP_READ) ] = {
1167 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1168 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1170 [ C(OP_WRITE) ] = {
1171 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1172 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
1174 [ C(OP_PREFETCH) ] = {
1175 [ C(RESULT_ACCESS) ] = 0x0,
1176 [ C(RESULT_MISS) ] = 0x0,
1186 [ C(LL ) ] = {
1187 [ C(OP_READ) ] = {
1188 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1190 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1193 [ C(OP_WRITE) ] = {
1194 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1196 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1199 [ C(OP_PREFETCH) ] = {
1200 [ C(RESULT_ACCESS) ] = 0x0,
1201 [ C(RESULT_MISS) ] = 0x0,
1204 [ C(NODE) ] = {
1205 [ C(OP_READ) ] = {
1206 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
1209 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
1213 [ C(OP_WRITE) ] = {
1214 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
1217 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
1221 [ C(OP_PREFETCH) ] = {
1222 [ C(RESULT_ACCESS) ] = 0x0,
1223 [ C(RESULT_MISS) ] = 0x0,
1233 [ C(L1D) ] = {
1234 [ C(OP_READ) ] = {
1235 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1236 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1238 [ C(OP_WRITE) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1240 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1242 [ C(OP_PREFETCH) ] = {
1243 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1244 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1247 [ C(L1I ) ] = {
1248 [ C(OP_READ) ] = {
1249 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1250 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1252 [ C(OP_WRITE) ] = {
1253 [ C(RESULT_ACCESS) ] = -1,
1254 [ C(RESULT_MISS) ] = -1,
1256 [ C(OP_PREFETCH) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x0,
1258 [ C(RESULT_MISS) ] = 0x0,
1261 [ C(LL ) ] = {
1262 [ C(OP_READ) ] = {
1264 [ C(RESULT_ACCESS) ] = 0x01b7,
1266 [ C(RESULT_MISS) ] = 0x01b7,
1272 [ C(OP_WRITE) ] = {
1274 [ C(RESULT_ACCESS) ] = 0x01b7,
1276 [ C(RESULT_MISS) ] = 0x01b7,
1278 [ C(OP_PREFETCH) ] = {
1280 [ C(RESULT_ACCESS) ] = 0x01b7,
1282 [ C(RESULT_MISS) ] = 0x01b7,
1285 [ C(DTLB) ] = {
1286 [ C(OP_READ) ] = {
1287 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1288 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1290 [ C(OP_WRITE) ] = {
1291 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1292 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1294 [ C(OP_PREFETCH) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x0,
1296 [ C(RESULT_MISS) ] = 0x0,
1299 [ C(ITLB) ] = {
1300 [ C(OP_READ) ] = {
1301 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1302 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1304 [ C(OP_WRITE) ] = {
1305 [ C(RESULT_ACCESS) ] = -1,
1306 [ C(RESULT_MISS) ] = -1,
1308 [ C(OP_PREFETCH) ] = {
1309 [ C(RESULT_ACCESS) ] = -1,
1310 [ C(RESULT_MISS) ] = -1,
1313 [ C(BPU ) ] = {
1314 [ C(OP_READ) ] = {
1315 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1316 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1318 [ C(OP_WRITE) ] = {
1319 [ C(RESULT_ACCESS) ] = -1,
1320 [ C(RESULT_MISS) ] = -1,
1322 [ C(OP_PREFETCH) ] = {
1323 [ C(RESULT_ACCESS) ] = -1,
1324 [ C(RESULT_MISS) ] = -1,
1327 [ C(NODE) ] = {
1328 [ C(OP_READ) ] = {
1329 [ C(RESULT_ACCESS) ] = 0x01b7,
1330 [ C(RESULT_MISS) ] = 0x01b7,
1332 [ C(OP_WRITE) ] = {
1333 [ C(RESULT_ACCESS) ] = 0x01b7,
1334 [ C(RESULT_MISS) ] = 0x01b7,
1336 [ C(OP_PREFETCH) ] = {
1337 [ C(RESULT_ACCESS) ] = 0x01b7,
1338 [ C(RESULT_MISS) ] = 0x01b7,
1381 [ C(LL ) ] = {
1382 [ C(OP_READ) ] = {
1383 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1384 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1386 [ C(OP_WRITE) ] = {
1387 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1388 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1390 [ C(OP_PREFETCH) ] = {
1391 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1392 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1395 [ C(NODE) ] = {
1396 [ C(OP_READ) ] = {
1397 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1398 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1400 [ C(OP_WRITE) ] = {
1401 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1402 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1404 [ C(OP_PREFETCH) ] = {
1405 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1406 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1416 [ C(L1D) ] = {
1417 [ C(OP_READ) ] = {
1418 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1419 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1421 [ C(OP_WRITE) ] = {
1422 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1423 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1425 [ C(OP_PREFETCH) ] = {
1426 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1427 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1430 [ C(L1I ) ] = {
1431 [ C(OP_READ) ] = {
1432 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1433 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1435 [ C(OP_WRITE) ] = {
1436 [ C(RESULT_ACCESS) ] = -1,
1437 [ C(RESULT_MISS) ] = -1,
1439 [ C(OP_PREFETCH) ] = {
1440 [ C(RESULT_ACCESS) ] = 0x0,
1441 [ C(RESULT_MISS) ] = 0x0,
1444 [ C(LL ) ] = {
1445 [ C(OP_READ) ] = {
1447 [ C(RESULT_ACCESS) ] = 0x01b7,
1449 [ C(RESULT_MISS) ] = 0x01b7,
1455 [ C(OP_WRITE) ] = {
1457 [ C(RESULT_ACCESS) ] = 0x01b7,
1459 [ C(RESULT_MISS) ] = 0x01b7,
1461 [ C(OP_PREFETCH) ] = {
1463 [ C(RESULT_ACCESS) ] = 0x01b7,
1465 [ C(RESULT_MISS) ] = 0x01b7,
1468 [ C(DTLB) ] = {
1469 [ C(OP_READ) ] = {
1470 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1471 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1473 [ C(OP_WRITE) ] = {
1474 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1475 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1477 [ C(OP_PREFETCH) ] = {
1478 [ C(RESULT_ACCESS) ] = 0x0,
1479 [ C(RESULT_MISS) ] = 0x0,
1482 [ C(ITLB) ] = {
1483 [ C(OP_READ) ] = {
1484 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1485 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1487 [ C(OP_WRITE) ] = {
1488 [ C(RESULT_ACCESS) ] = -1,
1489 [ C(RESULT_MISS) ] = -1,
1491 [ C(OP_PREFETCH) ] = {
1492 [ C(RESULT_ACCESS) ] = -1,
1493 [ C(RESULT_MISS) ] = -1,
1496 [ C(BPU ) ] = {
1497 [ C(OP_READ) ] = {
1498 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1499 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1501 [ C(OP_WRITE) ] = {
1502 [ C(RESULT_ACCESS) ] = -1,
1503 [ C(RESULT_MISS) ] = -1,
1505 [ C(OP_PREFETCH) ] = {
1506 [ C(RESULT_ACCESS) ] = -1,
1507 [ C(RESULT_MISS) ] = -1,
1510 [ C(NODE) ] = {
1511 [ C(OP_READ) ] = {
1512 [ C(RESULT_ACCESS) ] = 0x01b7,
1513 [ C(RESULT_MISS) ] = 0x01b7,
1515 [ C(OP_WRITE) ] = {
1516 [ C(RESULT_ACCESS) ] = 0x01b7,
1517 [ C(RESULT_MISS) ] = 0x01b7,
1519 [ C(OP_PREFETCH) ] = {
1520 [ C(RESULT_ACCESS) ] = 0x01b7,
1521 [ C(RESULT_MISS) ] = 0x01b7,
1531 [ C(L1D) ] = {
1532 [ C(OP_READ) ] = {
1533 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1534 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1536 [ C(OP_WRITE) ] = {
1537 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1538 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1540 [ C(OP_PREFETCH) ] = {
1541 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1542 [ C(RESULT_MISS) ] = 0,
1545 [ C(L1I ) ] = {
1546 [ C(OP_READ) ] = {
1547 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1548 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1550 [ C(OP_WRITE) ] = {
1551 [ C(RESULT_ACCESS) ] = -1,
1552 [ C(RESULT_MISS) ] = -1,
1554 [ C(OP_PREFETCH) ] = {
1555 [ C(RESULT_ACCESS) ] = 0,
1556 [ C(RESULT_MISS) ] = 0,
1559 [ C(LL ) ] = {
1560 [ C(OP_READ) ] = {
1561 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1562 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1564 [ C(OP_WRITE) ] = {
1565 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1566 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1568 [ C(OP_PREFETCH) ] = {
1569 [ C(RESULT_ACCESS) ] = 0,
1570 [ C(RESULT_MISS) ] = 0,
1573 [ C(DTLB) ] = {
1574 [ C(OP_READ) ] = {
1575 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1576 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1578 [ C(OP_WRITE) ] = {
1579 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1580 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1582 [ C(OP_PREFETCH) ] = {
1583 [ C(RESULT_ACCESS) ] = 0,
1584 [ C(RESULT_MISS) ] = 0,
1587 [ C(ITLB) ] = {
1588 [ C(OP_READ) ] = {
1589 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1590 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1592 [ C(OP_WRITE) ] = {
1593 [ C(RESULT_ACCESS) ] = -1,
1594 [ C(RESULT_MISS) ] = -1,
1596 [ C(OP_PREFETCH) ] = {
1597 [ C(RESULT_ACCESS) ] = -1,
1598 [ C(RESULT_MISS) ] = -1,
1601 [ C(BPU ) ] = {
1602 [ C(OP_READ) ] = {
1603 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1604 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1606 [ C(OP_WRITE) ] = {
1607 [ C(RESULT_ACCESS) ] = -1,
1608 [ C(RESULT_MISS) ] = -1,
1610 [ C(OP_PREFETCH) ] = {
1611 [ C(RESULT_ACCESS) ] = -1,
1612 [ C(RESULT_MISS) ] = -1,
1622 [ C(L1D) ] = {
1623 [ C(OP_READ) ] = {
1624 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1625 [ C(RESULT_MISS) ] = 0,
1627 [ C(OP_WRITE) ] = {
1628 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1629 [ C(RESULT_MISS) ] = 0,
1631 [ C(OP_PREFETCH) ] = {
1632 [ C(RESULT_ACCESS) ] = 0x0,
1633 [ C(RESULT_MISS) ] = 0,
1636 [ C(L1I ) ] = {
1637 [ C(OP_READ) ] = {
1638 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1639 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1641 [ C(OP_WRITE) ] = {
1642 [ C(RESULT_ACCESS) ] = -1,
1643 [ C(RESULT_MISS) ] = -1,
1645 [ C(OP_PREFETCH) ] = {
1646 [ C(RESULT_ACCESS) ] = 0,
1647 [ C(RESULT_MISS) ] = 0,
1650 [ C(LL ) ] = {
1651 [ C(OP_READ) ] = {
1652 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1653 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1655 [ C(OP_WRITE) ] = {
1656 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1657 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1659 [ C(OP_PREFETCH) ] = {
1660 [ C(RESULT_ACCESS) ] = 0,
1661 [ C(RESULT_MISS) ] = 0,
1664 [ C(DTLB) ] = {
1665 [ C(OP_READ) ] = {
1666 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1667 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1669 [ C(OP_WRITE) ] = {
1670 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1671 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1673 [ C(OP_PREFETCH) ] = {
1674 [ C(RESULT_ACCESS) ] = 0,
1675 [ C(RESULT_MISS) ] = 0,
1678 [ C(ITLB) ] = {
1679 [ C(OP_READ) ] = {
1680 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1681 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1683 [ C(OP_WRITE) ] = {
1684 [ C(RESULT_ACCESS) ] = -1,
1685 [ C(RESULT_MISS) ] = -1,
1687 [ C(OP_PREFETCH) ] = {
1688 [ C(RESULT_ACCESS) ] = -1,
1689 [ C(RESULT_MISS) ] = -1,
1692 [ C(BPU ) ] = {
1693 [ C(OP_READ) ] = {
1694 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1695 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1697 [ C(OP_WRITE) ] = {
1698 [ C(RESULT_ACCESS) ] = -1,
1699 [ C(RESULT_MISS) ] = -1,
1701 [ C(OP_PREFETCH) ] = {
1702 [ C(RESULT_ACCESS) ] = -1,
1703 [ C(RESULT_MISS) ] = -1,
1752 [ C(LL ) ] = {
1753 [ C(OP_READ) ] = {
1754 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1755 [ C(RESULT_MISS) ] = 0,
1757 [ C(OP_WRITE) ] = {
1758 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1759 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1761 [ C(OP_PREFETCH) ] = {
1762 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1763 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1773 [ C(L1D) ] = {
1774 [ C(OP_READ) ] = {
1775 [ C(RESULT_ACCESS) ] = 0,
1776 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1778 [ C(OP_WRITE) ] = {
1779 [ C(RESULT_ACCESS) ] = 0,
1780 [ C(RESULT_MISS) ] = 0,
1782 [ C(OP_PREFETCH) ] = {
1783 [ C(RESULT_ACCESS) ] = 0,
1784 [ C(RESULT_MISS) ] = 0,
1787 [ C(L1I ) ] = {
1788 [ C(OP_READ) ] = {
1789 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1790 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1792 [ C(OP_WRITE) ] = {
1793 [ C(RESULT_ACCESS) ] = -1,
1794 [ C(RESULT_MISS) ] = -1,
1796 [ C(OP_PREFETCH) ] = {
1797 [ C(RESULT_ACCESS) ] = 0,
1798 [ C(RESULT_MISS) ] = 0,
1801 [ C(LL ) ] = {
1802 [ C(OP_READ) ] = {
1804 [ C(RESULT_ACCESS) ] = 0x01b7,
1805 [ C(RESULT_MISS) ] = 0,
1807 [ C(OP_WRITE) ] = {
1809 [ C(RESULT_ACCESS) ] = 0x01b7,
1811 [ C(RESULT_MISS) ] = 0x01b7,
1813 [ C(OP_PREFETCH) ] = {
1815 [ C(RESULT_ACCESS) ] = 0x01b7,
1817 [ C(RESULT_MISS) ] = 0x01b7,
1820 [ C(DTLB) ] = {
1821 [ C(OP_READ) ] = {
1822 [ C(RESULT_ACCESS) ] = 0,
1823 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1825 [ C(OP_WRITE) ] = {
1826 [ C(RESULT_ACCESS) ] = 0,
1827 [ C(RESULT_MISS) ] = 0,
1829 [ C(OP_PREFETCH) ] = {
1830 [ C(RESULT_ACCESS) ] = 0,
1831 [ C(RESULT_MISS) ] = 0,
1834 [ C(ITLB) ] = {
1835 [ C(OP_READ) ] = {
1836 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1837 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1839 [ C(OP_WRITE) ] = {
1840 [ C(RESULT_ACCESS) ] = -1,
1841 [ C(RESULT_MISS) ] = -1,
1843 [ C(OP_PREFETCH) ] = {
1844 [ C(RESULT_ACCESS) ] = -1,
1845 [ C(RESULT_MISS) ] = -1,
1848 [ C(BPU ) ] = {
1849 [ C(OP_READ) ] = {
1850 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1851 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1853 [ C(OP_WRITE) ] = {
1854 [ C(RESULT_ACCESS) ] = -1,
1855 [ C(RESULT_MISS) ] = -1,
1857 [ C(OP_PREFETCH) ] = {
1858 [ C(RESULT_ACCESS) ] = -1,
1859 [ C(RESULT_MISS) ] = -1,
1907 [C(L1D)] = {
1908 [C(OP_READ)] = {
1909 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1910 [C(RESULT_MISS)] = 0x0,
1912 [C(OP_WRITE)] = {
1913 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1914 [C(RESULT_MISS)] = 0x0,
1916 [C(OP_PREFETCH)] = {
1917 [C(RESULT_ACCESS)] = 0x0,
1918 [C(RESULT_MISS)] = 0x0,
1921 [C(L1I)] = {
1922 [C(OP_READ)] = {
1923 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1924 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1926 [C(OP_WRITE)] = {
1927 [C(RESULT_ACCESS)] = -1,
1928 [C(RESULT_MISS)] = -1,
1930 [C(OP_PREFETCH)] = {
1931 [C(RESULT_ACCESS)] = 0x0,
1932 [C(RESULT_MISS)] = 0x0,
1935 [C(LL)] = {
1936 [C(OP_READ)] = {
1937 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1938 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1940 [C(OP_WRITE)] = {
1941 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1942 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1944 [C(OP_PREFETCH)] = {
1945 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1946 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1949 [C(DTLB)] = {
1950 [C(OP_READ)] = {
1951 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1952 [C(RESULT_MISS)] = 0x0,
1954 [C(OP_WRITE)] = {
1955 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1956 [C(RESULT_MISS)] = 0x0,
1958 [C(OP_PREFETCH)] = {
1959 [C(RESULT_ACCESS)] = 0x0,
1960 [C(RESULT_MISS)] = 0x0,
1963 [C(ITLB)] = {
1964 [C(OP_READ)] = {
1965 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1966 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1968 [C(OP_WRITE)] = {
1969 [C(RESULT_ACCESS)] = -1,
1970 [C(RESULT_MISS)] = -1,
1972 [C(OP_PREFETCH)] = {
1973 [C(RESULT_ACCESS)] = -1,
1974 [C(RESULT_MISS)] = -1,
1977 [C(BPU)] = {
1978 [C(OP_READ)] = {
1979 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1980 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1982 [C(OP_WRITE)] = {
1983 [C(RESULT_ACCESS)] = -1,
1984 [C(RESULT_MISS)] = -1,
1986 [C(OP_PREFETCH)] = {
1987 [C(RESULT_ACCESS)] = -1,
1988 [C(RESULT_MISS)] = -1,
1997 [C(LL)] = {
1998 [C(OP_READ)] = {
1999 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2001 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2004 [C(OP_WRITE)] = {
2005 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2007 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2010 [C(OP_PREFETCH)] = {
2011 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
2013 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
2023 [C(L1D)] = {
2024 [C(OP_READ)] = {
2025 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2026 [C(RESULT_MISS)] = 0x0,
2028 [C(OP_WRITE)] = {
2029 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2030 [C(RESULT_MISS)] = 0x0,
2032 [C(OP_PREFETCH)] = {
2033 [C(RESULT_ACCESS)] = 0x0,
2034 [C(RESULT_MISS)] = 0x0,
2037 [C(L1I)] = {
2038 [C(OP_READ)] = {
2039 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
2040 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
2042 [C(OP_WRITE)] = {
2043 [C(RESULT_ACCESS)] = -1,
2044 [C(RESULT_MISS)] = -1,
2046 [C(OP_PREFETCH)] = {
2047 [C(RESULT_ACCESS)] = 0x0,
2048 [C(RESULT_MISS)] = 0x0,
2051 [C(LL)] = {
2052 [C(OP_READ)] = {
2053 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2054 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2056 [C(OP_WRITE)] = {
2057 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
2058 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
2060 [C(OP_PREFETCH)] = {
2061 [C(RESULT_ACCESS)] = 0x0,
2062 [C(RESULT_MISS)] = 0x0,
2065 [C(DTLB)] = {
2066 [C(OP_READ)] = {
2067 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
2068 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
2070 [C(OP_WRITE)] = {
2071 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
2072 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
2074 [C(OP_PREFETCH)] = {
2075 [C(RESULT_ACCESS)] = 0x0,
2076 [C(RESULT_MISS)] = 0x0,
2079 [C(ITLB)] = {
2080 [C(OP_READ)] = {
2081 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
2082 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
2084 [C(OP_WRITE)] = {
2085 [C(RESULT_ACCESS)] = -1,
2086 [C(RESULT_MISS)] = -1,
2088 [C(OP_PREFETCH)] = {
2089 [C(RESULT_ACCESS)] = -1,
2090 [C(RESULT_MISS)] = -1,
2093 [C(BPU)] = {
2094 [C(OP_READ)] = {
2095 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
2096 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
2098 [C(OP_WRITE)] = {
2099 [C(RESULT_ACCESS)] = -1,
2100 [C(RESULT_MISS)] = -1,
2102 [C(OP_PREFETCH)] = {
2103 [C(RESULT_ACCESS)] = -1,
2104 [C(RESULT_MISS)] = -1,
2113 [C(LL)] = {
2114 [C(OP_READ)] = {
2115 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
2117 [C(RESULT_MISS)] = GLM_DEMAND_READ|
2120 [C(OP_WRITE)] = {
2121 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
2123 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
2126 [C(OP_PREFETCH)] = {
2127 [C(RESULT_ACCESS)] = 0x0,
2128 [C(RESULT_MISS)] = 0x0,
2145 [C(LL)] = {
2146 [C(OP_READ)] = {
2147 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
2149 [C(RESULT_MISS)] = TNT_DEMAND_READ|
2152 [C(OP_WRITE)] = {
2153 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
2155 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
2158 [C(OP_PREFETCH)] = {
2159 [C(RESULT_ACCESS)] = 0x0,
2160 [C(RESULT_MISS)] = 0x0,
2243 [C(LL)] = {
2244 [C(OP_READ)] = {
2245 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
2246 [C(RESULT_MISS)] = 0,
2248 [C(OP_WRITE)] = {
2249 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
2250 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
2252 [C(OP_PREFETCH)] = {
2253 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
2254 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
6334 hybrid_var(pmu, hw_cache_event_ids)[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init_grt()
6611 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()
6735 …hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MI… in intel_pmu_init()
6812 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ | in intel_pmu_init()
6814 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS| in intel_pmu_init()
6816 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ| in intel_pmu_init()
6818 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE| in intel_pmu_init()
6934 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1; in intel_pmu_init()